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Embedded Systems Lab

For the development of digital systems, modeling and simulation are important tools used in each development step at the necessary level of abstraction. In this simulation-centric lab, you will model, simulate, and synthesize digital circuits and systems using state of the art hardware description languages and modeling styles for various abstraction levels.

The lab is organized in two parts. The first part deals with modeling, simulation and synthesis of digital circuits using VHDL. Behavioral and structural modeling styles will be addressed as well as synthesizable description styles such as for finite state machines and datapaths.

The second part focuses on the system level by modeling and simulating complete digital systems using SystemC and Transaction Level Modeling (TLM). Starting with behavioral models communicating via signals, we will increase system complexity and raise the abstraction levels towards modeling of component interactions using transactions as defined by the TLM 2.0 standard.

Lecturers:

Time and Place:

Prerequisites:

The following prerequisites are mandatory for participation in this lab:

  • Experience with the C++ programming language, object oriented programming (OOP), and the Unified Modeling Language (UML).
  • Prior attendance of RO/TI2 or any other course on digital circuits and computer organization, e.g. a passed bachelor course.

Recommended Literature:

  • Peter J. Ashenden, "The Student's Guide to VHDL", Morgan Kaufmann, ISBN: 978-1558608658
  • Bjarne Stroustrup, "The C++ Programming Language", Addison Wesley, ISBN: 978-0321563842
  • David C. Black, Jack Donovan, Bill Bunton, Anna Keist, "SystemC: From the Ground Up", ISBN: 978-1489982667
  • SystemC Quickreference Card

Entry Test:

On the first date, there will be a short, written test to determine your eligibility. The test will take about 30 minutes and cover the prerequisites. By attending, students on the waiting list have the chance to get into the course if other students drop out.

Lecture Slides:

VHDL
SystemC

Exercises:

Note: Both Ex1 and Ex2 (VHDL) will be done on Monday, April 11th.

VHDL
SystemC

Schedule:

Date

Day

Time

Room

HDL

Topic

04.04.16

Monday

09:00 - 12:15

ITI 2.163

VHDL

Entry Examination,
and Introduction to VHDL

11.04.16

Monday

09:00 - 12:15

ITI 2.163

VHDL

Basic Modeling

18.04.16

Monday

09:00 - 12:15

ITI 2.163

VHDL

Dataflow Modeling

25.04.16

Monday

09:00 - 12:15

ITI 2.163

VHDL

Behavioral Modeling

02.05.16

Monday

09:00 - 12:15

ITI 2.163

VHDL

Structural Modeling

09.05.16

Monday

09:00 - 12:15

ITI 2.163

VHDL

VHDL Library Concept

23.05.16

Monday

09:00 - 12:15

ITI 2.163

VHDL

RTL Modeling

30.05.16

Monday

09:00 - 12:15

ITI 2.163

VHDL

Synthesis

06.06.16

Monday

09:00 - 12:15

ITI 2.163

VHDL,
SystemC

VHDL Test,
and SystemC Overview

13.06.16

Monday

09:00 - 12:15

ITI 2.163

SystemC

Modeling Transformational Systems,
SystemC Built-In Channels,
Events, Time, and Simulation Mechanism

20.06.16

Monday

09:00 - 12:15

ITI 2.163

SystemC

SystemC Communication

27.06.16

Monday

09:00 - 12:15

ITI 2.163

SystemC

Transaction Level Modeling

04.07.16

Monday

09:00 - 12:15

ITI 2.163

SystemC

Advanced TLM Aspects

11.07.16

Monday

09:00 - 12:15

ITI 2.163

SystemC

OSCI TLM Standard (Part 1)

18.07.16

Monday

09:00 - 12:15

ITI 2.163

SystemC

SystemC Test,
OSCI TLM Standard (Part 2)

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