Grundlagen der Rechnerarchitektur (Advanced Processor Architecture)

News

The exam date in spring 2012 as scheduled by the Prüfungsamt is March 14th, at 14:00.

The room is or will be announced on the following site:

http://www.vis.uni-stuttgart.de/lehre/pruefungen/grundlagenklausuren-der-informatik.html

This lecture covers advanced concepts in computer architecture. Beside classical concepts like processor design and manufacturing, performance evaluation and optimization, and computer arithmetic new trends are discussed like low power design. Low power design is essential in mobile computing and communication which is expected to be a dominating application of microprocessors in a few years.

Computation power is increasing by exploiting parallelism on all levels of computation. In this course we will discuss instruction level parallelism, thread level parallelism, multiprocessor systems and emerging many-core technologies found in current graphic accelerators.

The lecture provides a solid background for the courses:

Design & Test of Systems-on-a-Chip
Hardware Verification
Self-Testable Systems
Fault Tolerant Systems

Staff

Prof. Hans-Joachim Wunderlich office: 3.162, Pfaffenwaldring 47
Dipl.-Inf. Stefan Holst office: 3.164, Pfaffenwaldring 47
Dipl.-Inform. Claus Braun office: 3.171, Pfaffenwaldring 47
Dipl.-Inf. Laura Rodríguez Gómez office: 3.174, Pfaffenwaldring 47

Schedule and Material

Tuesdays, 9:45-11:15, Lecture in room V38.02
Thursdays, 9:45-11:15, Lecture/Exercises in room V38.02

Week	Date	Time	Room	Topic
17	Apr 26	09:45-11:15	V38.02	The Scope of Computer Architecture
Slides Chapter 1: Scope of Computer Architecture Slides Chapter 2: Technology
17	Apr 28	09:45-11:15	V38.02	Technology
Hakmi, A.-W. et al.: Programmable Deterministic Built-in Self-test Proc. of the International Test Conference (ITC) 2007 Jorge-Luis Sanchez-Ponz: Parallel BIST Techniques at Register Transfer Level (RTL), Master Thesis 2001 Zoellin, C. et al.: BIST Power Reduction Using Scan-Chain Disable in the Cell Processor Proc. of the International Test Conference (ITC) 2006 Kuo, W. and Kim, T.: An overview of manufacturing yield and reliability modeling for semiconductor products Proceedings of the IEEE, 1999, 87, pp. 1329-1344 Williams, T. and Brown, N.: Defect Level as a Function of Fault Coverage IEEE Transactions on Computers, 1981, C-30, pp. 987-988 J. Vial et al.: Yield Improvement, Fault-Tolerance to the Rescue? 14th IEEE International On-Line Testing Symposium (IOLTS) 2008, pp. 165-166
18	May 03	09:45-11:15	V38.02	Power and Performance
Slides Chapter 3: Power and Performance Problem Sheet 1: Technology Additional Material: Chip Fabrication, Test and Yield Chapter 14 of the book S. Hassoun, T. Sasao and R.K. Brayton: Logic Synthesis and Verification, Kluwer Academic Publishers, 2002, discusses static timing analysis (dealing with path delays and path sensitization). Many good references are also given for further reading. K. Singh, A. Wang, R. Brayton and A. Sangiovanni-Vincentelli: Timing optimization of combinational logic Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on, 1988, 282-285. McGeer, P.C.; Brayton, R.K.; Sangiovanni-Vincentelli, A.L.; Sahni, S.K.: Performance Enhancement Through the Generalized Bypass Transform Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on, Vol., Iss., 11-14 Nov 1991, pp 184-187. Keutzer, K.; Malik, S.; Saldanha, A.: Is Redundancy Necessary to Reduce Delay? Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol.10, Iss.4, Apr 1991, pp 427-435. Berman, C.L.; Hathaway, D.J.; LaPaugh, A.S.; Trevillyan, L.H.: Efficient Techniques for Timing Correction Circuits and Systems, 1990., IEEE International Symposium on, Vol., Iss., 1-3 May 1990, pp 415-419, vol.1. Touati, H.J.; Savoj, H.; Brayton, R.K.: Delay Optimization of Combinational Logic Circuits by Clustering and Partial Collapsing Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on, Vol., Iss., 11-14 Nov 1991, pp. 188-191. Eugene L. Lawler, Karl N. Levitt, James Turner: Module Clustering to Minimize Delay in Digital Networks IEEE Trans. on Computers, Vol.C-18, Number 1, pp. 47-57, Jan 1969. Gonzalez, R.; Gordon, B.M.; Horowitz, M.A.: Supply and Threshold Voltage Scaling for Low Power CMOS Solid-State Circuits, IEEE Journal of, Vol.32, Iss.8, Aug 1997, pp 1210-1216.
18	May 05	09:45-11:15	V38.02	Exercises: Technology
19	May 10	09:45-11:15	V38.02	Power and Performance
Problem Sheet 2: Power and Performance
19	May 12	09:45-11:15	V38.02	Power and Performance
20	May 17	09:45-11:15	V38.02	Power and Performance
20	May 19	09:45-11:15	V38.02	Power and Performance
21	May 24	09:45-11:15	V38.02	Exercises: Power and Performance
21	May 26	09:45-11:15	V38.02	Exercises: Power and Performance
22	May 31	09:45-11:15	V38.02	Exercises & Computer Arithmetic
Slides Chapter 4: Computer Arithmetic Appendix I of the book: Hennessy, Patterson: Computer Architecture - A Quantitative Approach 4th ed. Vojin G. Oklobdzija, Earl R. Barnes: Some optimal schemes for ALU implementation in VLSI technology Proc. 7th Symp. Comput. Arithmetic, 1985. Volder, J. E.: The CORDIC Trigonometric Computing Technique IRE Trans. on Electron. Computers, 1959, EC-8, 330-334. Naini, A.; Dhablania, A.; James, W. and Das Sarma, D.: 1 GHz HAL SPARC64R Dual Floating Point Unit with RAS features Computer Arithmetic, 2001. Proceedings. 15th IEEE Symposium on, 2001, 173-183 Oh, H.; Mueller et al.: A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor Solid-State Circuits, IEEE Journal of, 2006, 41, 759-771
22	Jun 02	Holiday
23	Jun 07	09:45-11:15	V38.02	Computer Arithmetic
23	Jun 09	09:45-11:15	V38.02	Computer Arithmetic
IBM Excursion Information
24	Holidays
25	Jun 21	09:45-11:15	V38.02	Computer Arithmetic
Problem Sheet 3: Computer Arithmetic
25	Jun 23	Holiday
26	Jun 28	09:45-11:15	V38.02	Exercises: Computer Arithmetic
26	Jun 30	09:45-11:15	V38.02	Exercises: Computer Arithmetic
27	Jul 05	09:45-11:15	V38.02	Computer Arithmetic
27	Jul 07	08:30-18:30		IBM Visit
High Performance Computing: Slides of Joerg Schick and his video. David Goldberg: What Every Computer Scientist Should Know About Floating-Point Arithmetic, ACM Computing Surveys, 1991.
28	Jul 12	09:45-11:15	V38.02	Exercises and Lecture: Computer Arithmetic
28	Jul 14	09:45-11:15	V38.02	Instruction Level Parallelism
Slides: Chapter 5 Instruction Level Parallelism
29	Jul 19	09:45-11:15	V38.02	Instruction Level Parallelism
Problem Sheet 4: ILP and Parallel Architectures
29	Jul 21	09:45-11:15	0.124	Instruction Level Parallelism
Slides: Chapter 6, 7 Memory and Parallel Computing
30	Jul 26	09:45-11:15	V38.02	Memory Hierarchy and Parallel Computing
30	Jul 28	09:45-11:15	V38.02	Exercises: ILP and Parallel Architectures