Zur Webseite der Uni Stuttgart

Hardware Verification and Quality Assessment (HVQA)

Kernveranstaltung der Vertiefungslinie Rechnerarchitektur im Diplomstudiengang Informatik.
INFOTECH: 3L+1E, 3rd semester course.

News

Exam: The oral exam will take place on Friday, July 26, 2013. Students who registered for the exam (except for Vertiefungslinien-Prüfungen) please contact our secretary to reserve a time slot.

Overview

Microelectronic systems are more and more used in mission critical applications such as automotive, avionics and medical systems. Since errors during the design as well as manufacturing defects in these systems cannot be completely avoided system correctness has to be verified or validated with highest confidence.

This lecture gives an introduction to design validation and verification techniques which are applied in different steps of the design flow of integrated circuits. A second focus of the lecture are manufacturing test methods for integrated circuits in order to detect structural defects introduced during the production of the chip.

In the lecture the following issues will be addressed:

  • Design validation
  • Formal verification methods
  • Defect analysis
  • Hardware test (design-for-test, fault simulation, test generation)

Staff and Organization

Lecture:

Exercises:

Schedule and Material

The lecture slides and additional material can be downloaded from this website. Please use the login and password provided in the lecture for the download. Relevant to the examination are the contents of the lecture and exercises, not the slides alone. The times and dates of future lectures are subject to change. Changes are announced in the lectures.

Date

Time

Room

Topic

Material

11.04.

Thu, 11:30

0.108

L1: Introduction

Slides: Introduction (final)

12.04.

Fri, 11:30

ITI Sem. room

L2: Fundamentals

Slides: Prerequirements 1 (final)

18.04.

Thu, 11:30

ITI Sem. room

L3: Fundamentals

Slides: Prerequirements 2 (final)

19.04.

Fri, 11:30

ITI Sem. room

E1: Boolean functions

Exercises: Sheet 1

25.04.

Thu, 11:30

ITI Sem. room

L4: Fundamentals

Slides: Prerequirements 3

Material SAT Solver (not relevant for exam)

26.04.

Fri, 11:30

ITI Sem. room

L5: Fundamentals

Slides: Prerequirements 4

03.05.

Fri, 11:30

ITI Sem. room

L6: Fundamentals 4

-

10.05.

Fri, 11:30

ITI Sem. room

L7: Fundamentals 4,
Validation

Slides: Prerequirements 5

16.05.

Thu, 11:30

ITI Sem. room

L8: Validation

Slides: Validation 1

17.05.

Fri, 11:30

ITI Sem. room

E2: SAT & BDDs

Exercises: Sheet 2

--

--

--

--

Holidays, no lectures!

31.05.

Fri, 11:30

ITI Sem. room

E3: BDDs

Exercises: Sheet 3

6.06.

Thu, 11:30

ITI Sem. room

L9: Validation

Slides: Validation 2

Material functional test generation (not relevant for exam)

7.06.

Fri, 11:30

ITI Sem. room

L10: Verification

Slides: Verification 1

13.06.

Thu, 11:30

ITI Sem. room

L11: Verification

Slides: Verification 2

14.06.

Fri, 11:30

ITI Sem. room

E4: Validation

Exercises: Sheet4

20.06.

Thu, 11:30

ITI Sem. room

L12: Verification

-

21.06.

Fri, 11:30

ITI Sem. room

E5: Verification

Exercises: Sheet 5

27.06.

Thu, 11:30

ITI Sem. room

L13: Test

Slides: Test 1

28.06.

Fri, 11:30

ITI Sem. room

E6: Verification

Exercises: Sheet 6

04.07.

Thu, 11:30

ITI Sem. room

L14: Test

Slides: Test 2
Mentor Graphics User defined/cell aware fault model

05.07.

Fri, 11:30

ITI Sem. room

E7: Verification/Test

Exercises: Sheet 6 and Yield

11.07.

Thu, 11:30

ITI Sem. room

L15: Test

Slides: Test 3

12.07.

Fri, 11:30

ITI Sem. room

L16: Test

-

18.07.

Thu, 11:30

ITI Sem. room

L17: Test

Slides: Test 4

19.07.

Fri, 11:30

ITI Sem. room

E8: Test

Exercises: Sheet 8

26.07.

Friday



Oral examination


Akzeptieren

Diese Webseite verwendet Cookies. Durch die Nutzung dieser Webseite erklären Sie sich damit einverstanden, dass Cookies gesetzt werden. Mehr erfahren, zum Datenschutz