Design and Test of Systems on Chip

Kernveranstaltung der Vertiefungslinie Rechnerarchitektur im Master-Studiengang Informatik, Master-Studiengang Softwaretechnik,
INFOTECH: 2L+2E, 3rd semester course.

News

Lab certificates can be picked up in ITI 3.162 every day 13.00-14.00

Exam date: 18.08.2014

Overview

Technological progress in designing and manufacturing integrated circuits allows the integration of complex microelectronic systems including processors, memory, application specific and analog circuits into a single chip. This trend dominates today's and future systems and their design process: Costly manual design of logic is replaced by a core-based design methodology.
Besides the different design styles, paradigms and standards the essential steps of automated design, test and programming of digital and mixed signal circuits are discussed. Exercises and labs serve to practice the use of commercial tools and designs.

In the lecture the following issues are be addressed:

• Overview over system design
• Reuse and cores
• Standards and platforms
• Elements of analog and mixed signal designs
• Design validation and verification
• Test and design for testability with the related standards
• Application and programming of embedded processors

Prerequisites: Advanced Processor Architectures

Staff and Organization

Lecture:

• Prof. H.-J. Wunderlich
• Prof. M. Berroth (Analog and Mixed Signal Part)

Exercises:

• Dipl.-Inf. L. Rodríguez Gómez (Digital Part)
• Dipl.-Ing. Martin Schmidt (Analog and Mixed Signal Part)

Exercise rules

• The exercises are graded with 7 points for the theory and 3 points for the practical part (10 points in total)
• The theoretical part of every task sheet must be solved prior to the according lab session and submitted in a hand written form by every single participant (no team work) by the deadline specified on the task sheet
  • no points are given for late submissions
  • please use the submission box at ITI (staircase, 2nd floor).
• In the theoretical part, please answer the questions precisely and briefly.
• The practical part of an exercise must be graded until the end of the following lab session (hard deadline).
• The practical tasks may be solved in groups of two students.
• For students' records, we advise to bring a printed copy of the task sheet to the exercise and ask the supervisor to sign it after grading.
• For consultations, please observe our office hours (published on supervisors' websites).

Grading and Exam

To participate in the written exam, the student must acquire a certificate (Schein) by successfully completing the exercises. Certificate (Schein) requirements:

• At least 50% of points
• Attendance at 7 out of 8 exercises

The written exam is closed book. No additional materials (lecture notes, pocket calculators, etc.) are allowed.

Literature

• Rochit Rajsuman, System-On-a-Chip: Design and Test, London: Artech House ed., 2000
• Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen VLSI Test Principles and Architectures - Design for Testability, Boston: Morgan Kaufmann Publishers, 2006
• Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng, Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon),  Morgan Kaufmann, 1 edition, 2009
• William K. Lam, Hardware Design Verification: Simulation and Formal Method-Based Approaches, Prentice Hall, 1 edition, 2005

Schedule and Material

Timing:

• Thursdays, 11:30-13:00
• Fridays, 11:30-13:00

Location:

• Lecture: Room Fridays: V47.04 (Pfaffenwaldring 47);  Thursdays: 0.108 (Computer science building)
• Exercises: Room 2.163 (ETI, Pfaffenwaldring 47, 2nd floor)

This schedule is not final and is subject to change!