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Design and Test of Systems on Chip

FPGA Chip

Kernveranstaltung der Vertiefungslinie Rechnerarchitektur im Master-Studiengang Informatik, Master-Studiengang Softwaretechnik,
INFOTECH: 2L+2E, 3rd semester course.

News

Lab certificates can be picked up in ITI 3.162 every day 13.00-14.00

Exam date: 18.08.2014

    Overview

    Technological progress in designing and manufacturing integrated circuits allows the integration of complex microelectronic systems including processors, memory, application specific and analog circuits into a single chip. This trend dominates today's and future systems and their design process: Costly manual design of logic is replaced by a core-based design methodology.
    Besides the different design styles, paradigms and standards the essential steps of automated design, test and programming of digital and mixed signal circuits are discussed. Exercises and labs serve to practice the use of commercial tools and designs.

    In the lecture the following issues are be addressed:

    • Overview over system design
    • Reuse and cores
    • Standards and platforms
    • Elements of analog and mixed signal designs
    • Design validation and verification
    • Test and design for testability with the related standards
    • Application and programming of embedded processors

    Prerequisites: Advanced Processor Architectures

    Staff and Organization

    Lecture:

    Exercises:

    Exercise rules

    • The exercises are graded with 7 points for the theory and 3 points for the practical part (10 points in total)
    • The theoretical part of every task sheet must be solved prior to the according lab session and submitted in a hand written form by every single participant (no team work) by the deadline specified on the task sheet
      • no points are given for late submissions
      • please use the submission box at ITI (staircase, 2nd floor).
    • In the theoretical part, please answer the questions precisely and briefly.
    • The practical part of an exercise must be graded until the end of the following lab session (hard deadline).
    • The practical tasks may be solved in groups of two students.
    • For students' records, we advise to bring a printed copy of the task sheet to the exercise and ask the supervisor to sign it after grading.
    • For consultations, please observe our office hours (published on supervisors' websites).

    Grading and Exam

    To participate in the written exam, the student must acquire a certificate (Schein) by successfully completing the exercises. Certificate (Schein) requirements:

    • At least 50% of points
    • Attendance at 7 out of 8 exercises

    The written exam is closed book. No additional materials (lecture notes, pocket calculators, etc.) are allowed.

    Literature

    • Rochit Rajsuman, System-On-a-Chip: Design and Test, London: Artech House ed., 2000
    • Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen VLSI Test Principles and Architectures - Design for Testability, Boston: Morgan Kaufmann Publishers, 2006
    • Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng, Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon),  Morgan Kaufmann, 1 edition, 2009
    • William K. Lam, Hardware Design Verification: Simulation and Formal Method-Based Approaches, Prentice Hall, 1 edition, 2005

    Schedule and Material

    Timing:

    • Thursdays, 11:30-13:00
    • Fridays, 11:30-13:00

    Location:

    This schedule is not final and is subject to change!

    Week

    Date

    Time

    Room

    Topic

    15

    Apr 10

    11:30-13:00

    0.108

    L1: Introduction

    Slides: Introduction

    15

    Apr 11

    11:30-13:00

    V47.04

    L2: Modeling

    Slides: Models

    16

    Apr 17

    11:30-13:00

    ITI 2.163

    E1: SystemC

    Task sheet: Exercise 1

    16

    Apr 18

    11:30-13:00

    Holiday

    17

    Apr 24

    11:30-13:00

    ITI 2.163

    E2: System Level D&V

    Task sheet: Exercise 2

    17

    Apr 25

    11:30-13:00

    V47.04

    L3: Modeling

    Slides: Models

    18

    May 1

    -

    -

    Holiday

    18

    May 2

    11:30-13:00

    V47.04

    L4: System Validation

    Slides: Models and System Validation

    19

    May 8

    11:30-13:00

    ITI 2.163

    E3: Logic D&V

    Task Sheet: Exercise 3

    19

    May 9

    11:30-13:00

    V47.04

    L5: System Validation

    Slides:  System Validation

    GPU Simulation papers:

    1. Parallel Simulation of Apoptotic Receptor-Clustering on GPGPU Many-Core Architectures
    Braun, C., Daub, M., Schöll, A., Schneider, G. and Wunderlich, H.-J.
    Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine (BIBM'12), pp. 1-6 [PDF]

    2. Acceleration of Monte-Carlo Molecular Simulations on Hybrid Computing Architectures
    Braun, C., Holst, S., Wunderlich, H.-J., Castillo, J.M. and Gross, J.
    Proceedings of the 30th IEEE International Conference on Computer Design (ICCD'12), pp. 207-212 [PDF]

    20

    May 15

    11:30-13:00

    0.108

    L6: System Validation

    Slides:  System Validation (Emulation and Prototyping) and System Verification

    20

    May 16

    11:30-13:00

    V47.04

    L7: System Analysis

    Slides: System Validation (Non-functional Properties)

    21

    May 22

    11:30-13:00

    ITI 2.163

    E4: Mixed level simulation

    Task Sheet: Exercise 4

    21

    May 23

    11:30-13:00

    V47.04

    L8:Test

    Slides: Test: Fault Modeling & Simulation; Pattern Generation

    May 26/27

    ITI 2.163

    E5: Post-synthesis Validation

    Task Sheet: Exercise 5

    22

    May 29

    -

    -

    Holiday

    22

    May 30

    11:30-13:00

    No lecture

    23

    Jun 5

    11:30-13:00

    0.108

    L7: Analog/Mixed Signal 1

    Analog/Mixed Signal: 4.0, 4.1 , 4.2 ,4.3, 4.4, and 4.5

    23

    Jun 6

    11:30-13:00

    V57.04

    L8: Analog/Mixed Signal 2

    Analog/Mixed Signal

    24

    Jun 12

    -

    -

    No lectures

    24

    Jun 13

    -

    -

    No lectures

    25

    Jun 19

    -

    -

    Holiday

    25

    Jun 20

    11:30-13:00

    V47.04

    L9: Analog/Mixed Signal 3

    Analog/Mixed Signal 

    26

    Jun 26

    11:30-13:00

    0.108

    E6: Analog/Mixed Signal 4

    Analog/Mixed Signal: exercise 6 and things to know for the exam

    26

    Jun 27

    11:30-13:00

    V47.04

    L10: Test

    Slides: Pattern Generation and Design-for-Test

    27

    Jul 3

    11:30-13:00

    ITI 2.163

    E7: Scan design

    Task Sheet: Exercise 7

    27

    Jul 4

    11:30-13:00

    V47.04

    L11: BIST

    Slides: BIST

    28

    Jul 10

    11:30-13:00

    ITI 2.163

    E8: ATPG and BIST

    Task Sheet: Exercise 8

    28

    Jul 11

    11:30-13:00

    V47.04

    L12: Test standards

    Slides: Test standards

    29

    Jul 17

    11:30-13:00

    ITI 2.163

    Lab

    29

    Jul 18

    11:30-13:00

    V47.04

    Mock exam, Q&A

    Mock exam

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