Zur Webseite der Uni Stuttgart

Elements of High-Performance RISC Processors - Design and Synthesis

Cell die photo

News

    Attendance is MANDATORY in this course.

    Lab Course Overview

    In this lab course a basic 32-bit RISC processor is extended with techniques common to high-performance processors.

    The  extensions include:

    • Pipelining, forwarding
    • 4-way SIMD
    • Pipelined hardware multiplier
    • Cache, writeback queue, etc.

    The resulting processor architecture is quite similar to the one used in the synergistic processing element of the Cell Broadband Engine, used e.g. in Playstation 3.

    In order to achieve high performance,  proper design techniques and software tools for synthesis and analysis play an important role. The students learn how timing analysis, pipelining and retiming can be used to optimize the synthesis results. Finally, the processor is emulated on a Virtex-5 FPGA prototyping board.

    The performance gain of the student's design is measured for the Mandelbrot set computation with respect to the basic RISC architecture. Because software has to be specifically tailored to high-performance processor architectures, the lab course also deals with scheduling techniques that avoid pipeline stalls.

    Schedule

    Number

    Exercise

    Due Date Theory

    Due Date Practical Part

    Material/Comments

    01

    Task sheet

    -

    21.04.2015

    Introduction

    02

    Task sheet

    17.04.2015

    28.04.2015

    VHDL

    03

    Task sheet

    24.04.2015

    05.05.2015

    Assembler

    04

    Task sheet

    04.05.2015

    19.05.2015

    05

    Task sheet

    08.05.2015

    19.05.2015

    06

    Task sheet

    15.05.2015

    02.06.2015

    07

    Task sheet

    29.05.2015

    16.06.2015

    08

    Task sheet

    12.06.2015

    23.06.2015

    09

    Task sheet

    19.06.2015

    30.06.2015

    10

    Task sheet

    -

    07.07.2015

    Test round 1

    -

    07.07.2015

    Test round 2

    -

    14.07.2015

    Presentations

    -

    21.07.2105

    Literature

    • D. A. Patterson, J. L. Hennessy: Computer Organization & Design . The Hardware / Software Interface (3rd Edition); San Francisco, Ca.: Morgan Kaufmann Publishers Inc., 2004
    • J. L. Hennessy and D. A. Patterson: Computer Architecture - A Quantitative Approach (5th Edition); San Francisco, Ca.: Morgan Kaufmann Publishers Inc., 2012

    Tutors

    Akzeptieren

    Diese Webseite verwendet Cookies. Durch die Nutzung dieser Webseite erklären Sie sich damit einverstanden, dass Cookies gesetzt werden. Mehr erfahren, zum Datenschutz