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Hardware Verification and Quality Assessment (HVQA)

Kernveranstaltung der Vertiefungslinie Rechnerarchitektur im Diplom- und Masterstudiengang Informatik.
INFOTECH: 3L+1E, 3rd semester course.

News

Exam on September 1st. 

Overview

Microelectronic systems are more and more used in mission critical applications such as automotive, avionics and medical systems. Since errors during the design as well as manufacturing defects in these systems cannot be completely avoided system correctness has to be verified or validated with highest confidence.

This lecture gives an introduction to design validation and verification techniques which are applied in different steps of the design flow of integrated circuits. A second focus of the lecture are manufacturing test methods for integrated circuits in order to detect structural defects introduced during the production of the chip.

In the lecture the following issues will be addressed:

  • Design validation
  • Formal verification methods
  • Defect analysis
  • Hardware test (design-for-test, fault simulation, test generation)

Staff and Organization

Lecture:

Exercises:

Schedule and Material

  • Lecture: Thursday,15:45-17:15(biweekly) in V47.06 ; Friday, 11:30-13:00 in V47.04
  • Exercises: Thursdays (biweekly), 15:45-17:15 in V47.06

The lecture slides and additional material can be downloaded from this website. Please use the login and password provided in the lecture for the download. Relevant to the examination are the contents of the lecture and exercises, not the slides alone. The times and dates of future lectures are subject to change. Changes are announced in the lectures.

Date

Time

Room

Topic

16.04.

Thu, 15:45

V47.06

L1: Introduction

17.04.

Fri, 11:30

V47.04

L2: Formal basics: Boolean Algebra & Cube Calculus

23.04.

Thu, 15:45

V47.06

L3: Formal basics: Boolean Algebra & Cube Calculus

24.04.

Fri, 11:30

V47.04

E1: Boolean functions and relations

30.04.

Thu, 15:45

V7.23

L4: SAT

07.05.

Thu, 15:45

V47.06

L5: SAT and Graph-based representations

08.05.

Fri, 11:30

V47.04

E2: SAT & BDDs

15.05.

Fri, 11:30

V47.04

L6: Validation: Layout & Switch Level

21.05.

Thu, 15:45

V47.06

L7: Validation: Gate & RTL level

22.05.

Fri, 11:30

V47.04

L8: Validation: Accelerated Sim, Emulation & Functional Test

05.06.

Fri, 11:30

V47.04

E3: Validation

11.06.

Thu, 15:45

V47.06

L9: Verification: Timing and Equivalence Checking

12.06.

Fri, 11:30

V9.31

L10: Verification: Model Checking 1

18.06.

Thu, 15:45

V47.06

L11: Verification: Model Checking 2

19.06.

Fri, 11:30

V47.04

E4: Verification

25.06.

Thu, 15:45

V47.06

L12: Test: Yield and Defect Analysis

26.06.

Fri, 11:30

V47.04

L13: Test: Fault Modeling

02.07.

Thu, 15:45

PWR 9.12

L14: Test: Fault simulation

03.07.

Fri, 11:30

V47.04

L15: Test: ATPG

09.07.

Thu, 15:45

V47.06

E4: Mock Exam

10.07.

Fri, 11:30

V47.04

E5: Discussion of mock exam, ex 4 and ex 5

16.07.

Thu, 15:45

V47.06

L16: Test: BDD-ATPG, SAT-ATPG and sequential ATPG

17.07.

Fri, 11:30

V47.04

L17: Test: Iddq test & Scan basics

23.07.

Thu, 15:45

V47.06

L18: Test: Test Compression

24.07.

Fri, 11:30

V47.04

L19: Test: BIST & Test Standards


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