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Into Darkness: Challenges in the Dark Silicon Era

For decades, semiconductor technology scaling enabled the design and production of CMOS devices which comprised more, smaller, and faster transistors in each new technology generation. The so-called Dennard scaling allowed the reduction of threshold and supply voltage in accordance with the decreasing feature sizes. As a consequence, the required switching power of the transistors was also reduced and the overall power density of such devices was kept almost constant.

Unfortunately, with the advance into modern deep nanometer semiconductor technology nodes, leakage power emerged as a dominating factor and it became evident, that the transistor power consumption does no longer scale in accordance with the integration density. As a consequence, it will no longer be possible to switch on simultaneously all transistors that can be integrated on a chip, at least not if power and cooling budgets have to be kept.

Due to these fundamental developments, semiconductor technology is therefore now entering the so-called Era of Dark Silicon. Current predictions state that for the 8nm technology node up to 50% of the silicon will be dark, which means that only half of the transistors that can be integrated can actually be used at the same time.

Dark Silicon induces major challenges in all areas of modern semiconductor technology and electronic design automation. This seminar will cover some of the most important challenges in the context of:

  • Processor and memory architectures
  • Design and implementation of circuits
  • Verification and validation
  • Test and diagnosis
  • Software and application development

 

Schedule and Location:

  • Room: 0.108 -> 3.175 (ETI, Pfaffenwaldring 47)
  • Time: Monday, 09:45 - 11:15

News:

  • 03.06.2016: Schedule and venue updated.
  • 25.05.2016: Schedule updated.
  • Presenters have been assigned to topics in schedule
  • Slides from first meeting are available now
  • Password issues fixed

Templates:

  • LaTeX-Template for report (.zip)
  • PowerPoint template for presentation (.potx)

Schedule

 

Preliminary schedule (subject to changes):

Date

Room

Topic

04.04.2016

0.108

Introduction, topic overview and assignment (Slides)

18.04.2016

---

25.04.2016

0.108

Introductory Session

Challenges in the Dark Silicon Era (Slides)
Presenter: Claus Braun

02.05.2016

---

09.05.2016

---

23.05.2016

---

30.05.2016

0.108

Session 1: Design Aspects of Dark Silicon

Topic 2: Near-Threshold Design (Report, Slides)
Presenter: Bahadir Gün, Supervisor: Eric Schneider

06.06.2016

3.175

Session 2: Power Management in Dark Silicon

Topic 3: Power and Voltage Regulation (Report, Slides)
Presenter: Ruthra Kumar Ravi Sulochana, Supervisor: Eric Schneider

13.06.2016

3.175

Session 3: Architectures for Dark Silicon

Topic 6: Variable Precision for Low Power Consumption (Report, Slides)
Presenter: Bannur Amitkumar, Supervisor: Claus Braun

20.06.2016

3.175

Session 4: Memory Communication on Dark Silicon

Topic 5: Specialized-purpose Cores (Report, Slides)
Presenter: Gasim Mammadov, Supervisor: Alexander Schöll

Topic 7: Memory and Communication Architectures (Report, Slides)
Presenter: Govind Balakrishnan, Supervisor: Claus Braun

27.06.2016

---

04.07.2016

---

11.07.2016

Session 5: Network-on-Chips on Dark Silicon

Topic 10: Computational Sprinting (Report, Slides)
Presenter: Jai Vighneshwar Jayakumar, Supervisor: Alexander Schöll

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