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Hardware Verification and Quality Assessment (HVQA)

Kernveranstaltung der Vertiefungslinie Rechnerarchitektur im Masterstudiengang Informatik.
INFOTECH: 3L+1E, 3rd semester course.

News

The exam check will take place on Tuesday, August 1st from 4 to 5PM in the ITI department (Pfaffenwaldring 47, 3rd floor).

 

Written HVQA Exam takes place on Fri, July 28 2017, 11-13 o'clock, V55.01.

(Written 90 min exam)

  • Closed book exam, no materials (no script, no calculator, no smartphone...) allowed
  • Please use a non-erasable pen (not red or green, no pencil)
  • Paper will be provided from our side)

Link to ILIAS Course website(join with password from first lecture).

Overview

Micro- and nano-electronic systems are more and more used in safety-critical applications such as automotive, avionics and medical systems. Since errors during the design as well as manufacturing defects in these systems cannot be completely avoided, system correctness has to be verified or validated with highest confidence.

This lecture gives an introduction to design validation and verification techniques that are applied in different steps of the design flow of integrated circuits. A second focus of the lecture are manufacturing test methods for integrated circuits in order to detect structural defects introduced during the production of the chip.

In the lecture the following issues will be addressed:

  • Design validation
  • Formal verification methods
  • Defect analysis
  • Hardware test (design-for-test, fault simulation, test generation)

Staff and Organization

Lecture:

Exercises:

Schedule and Material

  • Lecture and exercise appointments:
    Thursday 15:45-17:15 o'clock, V47.06
    Friday 11:30-13:00 o'clock, V47.04 
  • Link to ILIAS course website

The lecture slides and additional material can be downloaded from the ILIAS course website. Please join the ILIAS course with the password provided in the lecture. Relevant to the examination are the contents of the lecture and exercises, not the slides alone. The times and dates of future lectures are subject to change. Changes are announced in the lectures.

Date

Time

Room

Topic

Thu, April 13

15:45-17:15

V47.06

Introduction

Fri, April 14 (holiday)

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--

--

Thu, April 20

15:45-17:15

V47.06

Formal Basics (Functions)

Fri, April 21

11:30-13:00

V47.04

Formal Basics (Cubes)

Thu, April 27

15:45-17:15

V47.06

Formal Basics (SAT)

Fri, April 28

11:30-13:00

V47.04

Exercise 1

Thu, May 4

15:45-17:15

V47.06

Formal Basics (Graphs)

Fri, May 5

11:30-13:00

V47.04

Exercise 1 contd.

Thu, May 11

15:45-17:15

V47.06

Formal Basics (Graphs), Validation

Fri, May 12

11:30-13:00

V47.04

Validation, Simulation

Thu, May 18

15:45-17:15

V47.06

Validation, Simulation

Fri, May 19

11:30-13:00

V47.04

Exercise 2

Thu, May 25 (holiday)

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--

--

Fri, May 26

11:30-13:00

V47.04

Exercise 2,3

Thu, June 1

15:45-17:15

V47.06

Validation, Emulation

Fri, June 2

11:30-13:00

V47.04

Verification

Thu, June 8 (no lecture)

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--

Fri, June 9 (no lecture)

--

--

--

Thu, June 15 (holiday)

--

--

--

Fri, June 16

11:30-13:00

V47.04

Exercise 3

Thu, June 22

15:45-17:15

V47.06

Verification

Fri, June 23

11:30-13:00

V47.04

Verification

Thu, June 29

15:45-17:15

V47.06

Verification, Test

Fri, June 30

11:30-13:00

V47.04

Test

Thu, July 6

15:45-17:15

V7.41

Exercise 4
(Room change to V7.41 due to Bauigelfest)

Fri, July 7

11:30-13:00

V47.04

Test

Thu, July 13

15:45-17:15

V47.06

Test

Fri, July 14

11:30-13:00

V47.04

Test

Thu, July 20

15:45-17:15

V47.06

Test

Fri, July 21

11:30-13:00

V47.04

Exercise 5

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