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Elements of High-Performance RISC Processors - Design and Synthesis

Cell die photo

News

    • The open lab session takes place every Wednesday from 2 pm to 6 pm, and every Thursday from 10 am to 2 pm.
    • If you do not need to experiment with the FPGA board, please use the ITI computer pool in 3rd floor at any time (you can also access our computer pool remotely - see introductory slides)

    Lab Course Overview

    In this lab course a basic 32-bit RISC processor is extended with techniques common to high-performance processors.

    The  extensions include:

    • Pipelining, forwarding
    • 4-way SIMD
    • Pipelined hardware multiplier
    • Cache, writeback queue, etc.

    The resulting processor architecture is quite similar to the one used in the synergistic processing element of the Cell Broadband Engine, used e.g. in Playstation 3.

    In order to achieve high performance,  proper design techniques and software tools for synthesis and analysis play an important role. The students learn how timing analysis, pipelining and retiming can be used to optimize the synthesis results. Finally, the processor is emulated on a Virtex-5 FPGA prototyping board.

    The performance gain of the student's design is measured for the Mandelbrot set computation with respect to the basic RISC architecture. Because software has to be specifically tailored to high-performance processor architectures, the lab course also deals with scheduling techniques that avoid pipeline stalls.

    Schedule

    Number

    Exercise

    Due Date Theory

    Due Date Practical Part

    Material/Comments

    01

    Task Sheet

    -

    25.10.2013

    Introduction

    02

    Task Sheet

    25.10.2013

    8.11.2013

    VHDL

    03

    Task Sheet

    8.11.2013

    15.11.2013

    Assembler

    04

    Task Sheet

    15.11.2013

    29.11.2013

    05

    Task Sheet

    22.11.2013

    6.12.2013

    06

    Task Sheet

    6.12.2013

    13.12.2013

    07

    Task Sheet

    13.12.2013

    17.01.2013

    08

    Task Sheet

    20.12.2013

    24.01.2014

    09

    Task Sheet

    24.01.2014

    31.01.2014

    10

    Task Sheet

    -

    -

    Final test, round 1

    31.01.2014

    Final test, round 2

    07.02.2014

    Presentations

    07.02.2014

    Literature

    • D. A. Patterson, J. L. Hennessy: Computer Organization & Design . The Hardware / Software Interface (3rd Edition); San Francisco, Ca.: Morgan Kaufmann Publishers Inc., 2004
    • J. L. Hennessy and D. A. Patterson: Computer Architecture - A Quantitative Approach (5th Edition); San Francisco, Ca.: Morgan Kaufmann Publishers Inc., 2012

    Tutors

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