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Design & Test of 3D-integrated circuits

Overview

The pin count of a chip and the length of interconnects on a circuit board may limit the integration of functions in the system. The three-dimensional stacking of chips allows the dense integration and interconnection of both homogenous and heterogeneous functionality by using through-silicon-vias (interconnects).

This recent 3D-IC trend poses novel challenges to electronic design automation tools and manufacturing techniques. Synthesis algorithms traditionally only consider a two-dimensional layout. The tight stacking of chips increases power density in the system and may cause temperature hot spots which threaten reliability of the system.

During the manufacturing of the chips and the through-silicon-vias, defects may occur which need to be tested and diagnosed to avoid assembly of defective units. Such a test must both be very thorough and cost-efficient. Spare vias can be integrated to tolerate certain defects and to increase the yield.

This seminar addresses the challenges posed by 3D-IC integration and discusses algorithmic solutions to them. This comprises methods tailored for 3D-IC targeting:

• Design automation and synthesis

• Simulation algorithms

• Power and thermal management

• Test and diagnosis

• Yield and reliability challenges

The first meeting takes place on Wed, Oct 15th, 2014 from 09:45-11:15 o'clock in room 0.363 (comp. science building 38). 

Links

 

Schedule

 

Date

Topic

Supervisor

Student

Dec 3, 2014

1) ---

--

--

Dec 3, 2014

2) Via Modeling

D. Ull

J. Zhao

Dec 10, 2014

3) Floorplanning of 3D ICs by Simulated Annealing

R. Baranowski

F. Li

Dec 10, 2014

4) Design-for-Test: Scan Chain Synthesis

R. Baranowski

A. Vijayakrishnan

Dec 17, 2014

5) ---

--

--

Dec 17, 2014

6) Fault Models for 3D-Integrated Circuits

E. Schneider

A. Frosi

Jan 14, 2015

7) 3-D IC Yield Analysis and Optimization

M. Kochte

P. Adusumilli

Jan 14, 2015

8) Power and Thermal Modeling

D. Ull

T. Nguyen

Jan 21, 2015

10) Through-Silicon-Via (TSV) Repair

M. Kochte

S. Brandhofer

Jan 28, 2015

--

Jan 28, 2015

12) 3D integration of processor caches

D. Ull

B. K Ranganathappa

Feb 4, 2015

--

Feb 11, 2015

11) Test Scheduling and Test Power Consideration

M. Kochte

T. Musharraf

Feb 11, 2015

9) Diagnosis of 3D-Integrated Circuits

E. Schneider

A. Kuzmina

Staff

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