The CMOS technology downscales over and over, semiconductor companies have shipped devices of 14 nm technology in 2014. According to the international technology roadmap, in today’s nanometer era, random delay defects will more likely cause failure.

The simple example below demonstrates how a delay defect may alter the intended circuit operation: You have designed your circuit with specific timing constraints and considered slacks to protect your design against uncertainties. However, it is not working as intended.

Delay test is used to detect timing related failures. Small delay defects do not cause sufficient delay increments which produce timing failures and hence cannot be detected by the traditional delay test methods. Testing ICs at-speed to detect small delay defects is thus highly effective to get to the root of these kind of failures.

This seminar covers the following topics, looking into the concept, challenges and advanced techniques for at-speed testing of small delay defects:

• Test and diagnosis methods
• Built-in Self-test
• Faster-than at-speed test
• Clock generation and power issues
• Yield and reliability issues

Next Event: Thursday January 21, 11:30-13:00 (two talks). -- Schedule updated.

Next Event: Thursday December 10, 11:30-13:00 (one talk).

Next Event: Thursday October 22, 11:30-13:00, Introduction talk: Overview of Delay Fault Testing 

Room number: 3.175, Institut für Technische Informatik (ITI), Pfaffenwaldring 47.