Zur Webseite der Uni Stuttgart

At-speed Test and Diagnosis of Small Delay Defects in Advanced Nanometer Technologies

 

The CMOS technology downscales over and over, semiconductor companies have shipped devices of 14 nm technology in 2014. According to the international technology roadmap, in today’s nanometer era, random delay defects will more likely cause failure.

The simple example below demonstrates how a delay defect may alter the intended circuit operation: You have designed your circuit with specific timing constraints and considered slacks to protect your design against uncertainties. However, it is not working as intended.

 

 

Delay test is used to detect timing related failures. Small delay defects do not cause sufficient delay increments which produce timing failures and hence cannot be detected by the traditional delay test methods. Testing ICs at-speed to detect small delay defects is thus highly effective to get to the root of these kind of failures.

This seminar covers the following topics, looking into the concept, challenges and advanced techniques for at-speed testing of small delay defects:

  • Test and diagnosis methods
  • Built-in Self-test
  • Faster-than at-speed test
  • Clock generation and power issues
  • Yield and reliability issues

 

Next Event: Thursday January 21, 11:30-13:00 (two talks). -- Schedule updated.

Next Event: Thursday December 10, 11:30-13:00 (one talk).

Next Event: Thursday October 22, 11:30-13:00, Introduction talk: Overview of Delay Fault Testing 

 

Room number: 3.175, Institut für Technische Informatik (ITI), Pfaffenwaldring 47.

 

Schedule

 

The first meeting takes place on Monday, October 12th, 2015 from 15:45-17:15 o'clock.

Participation is mandatory. 

Date

Room

Topic

Supervisor

Student

Oct 12, 2015

0.363

Seminar requirements, rules and flow - topics description and assignment: Slides

Oct 22, 2015

3.175

Introduction talk: Overview of Delay Fault Testing: Slides

Oct 29, 2015

--

Nov 05, 2015

--

Nov 12, 2015

--

Nov 19, 2015


3.175

Simulation of Small Delay Defects (1)

Schneider

Test Pattern Generation Methods for Small Delay Defects (2)

Dalirsani

Nov 26, 2015

--

Dec 3, 2015


3.175

Robust and Hazard-Free Test Generation for Small Delay Defects (3)

Dalirsani

Nearly Robust Test Generation (4)

Dalirsani

Dec 10, 2015


3.175

Modeling of Delay Faults (5)

Slides Report

Dalirsani

Valentin Mihalcut

Deterministic Diagnosis of Small Delay Defects (6)

Schneider

Dec 17, 2015


3.175

Small Delay Defect Diagnosis based on Statistical Timing Analysis (7)

Dalirsani

cancelled

Faster-Than At-Speed Test (8)

Liu

Jan 07, 2015

--

Jan 14, 2016

--

Jan 21, 2016

3.175

Power-Noise/IR-Drop Reduction (12)

Slides Report

Schneider

Duc Toan Truong

On-Chip Clock Generation (10)

Slides Report Figures

Liu

Muhammad Tarique Saleem

Jan 28, 2016


3.175

On-Chip Delay Measurement (9)

Slides Report

Liu

Qi Zhang

Feb 04, 2016

3.175

Shift-Power Reduction in BIST (11)

Schneider 

 

 

 Topics and Literature List: PDF File

 

 

Guidelines

 

 

Akzeptieren

Diese Webseite verwendet Cookies. Durch die Nutzung dieser Webseite erklären Sie sich damit einverstanden, dass Cookies gesetzt werden. Mehr erfahren, zum Datenschutz