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ACCESS: Verification, Test, and Diagnosis of Advanced Scan Infrastructures

since 08.2014, DFG-Project: WU 245/17-1   

Project Description

VLSI designs incorporate specialized instrumentation for post-silicon validation and debug, volume test and diagnosis, as well as in-field system maintenance. Examples of instruments for efficient localization of silicon defects and design bugs include trace buffers, performance monitors, event counters, or scan chains. Test instrumentation includes test controllers, test wrappers, scan chains and structures for pattern decompression and compaction. Such instruments are used both in manufacturing test and for in-field test. Maintenance instrumentation is mainly used in regular system operation for monitoring, error detection, and reliability management. It includes, for instance, error monitors, memory repair controllers, and structures for system reprogramming and reconfiguration. Instruments for manufacturability, e.g. process monitors, facilitate the monitoring of chip performance and reliability. Due to the increasing complexity, however, the embedded infrastructure and access mechanisms themselves become a dependability bottleneck.

While efficient verification, test, and diagnosis techniques exist for combinational and some classes of sequential circuits, Reconfigurable Scan Networks (RSNs) still pose a serious challenge. RSNs are controlled via a serial interface and exhibit deeply sequential behavior (cf. IJTAG, IEEE Std 1687). Due to complex combinational and sequential dependencies, RSNs are beyond the capabilities of existing algorithms for verification, test, and diagnosis which were developed for classical, non-reconfigurable scan networks. The goal of ACCESS is to establish a methodology for efficient verification, test and diagnosis of RSNs to meet stringent reliability, safety and security goals. This comprises:

  • Unified RSN Modeling
  • Verification of Model Consistency
  • Formal Verification to guarantee operability, safety, and security
  • Efficient Test Generation and Fault Simulation
  • Post-Manufacture and In-Field Test
  • Diagnosis of Scan Infrastructure Faults
  • Robust Access to Faulty Scan Infrastructure

 This work is supported by the German Research Foundation (DFG) under grant WU 245/17-1 (2014-2017).


 Preliminary work in this field includes:

  • Verifikation Rekonfigurierbarer Scan-Netze
    Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
    Proc. 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014), Böblingen, Germany , Mar 10-12
  • Securing Access to Reconfigurable Scan Networks
    Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
    Proceedings of the 22nd IEEE Asian Test Symposium (ATS'13), Yilan, Taiwan, 18--21 Nov
  • Scan Pattern Retargeting and Merging with Reduced Access Time
    Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
    Proceedings of IEEE European Test Symposium (ETS'13), Avignon, France, May 27-30 , pp. 39-45
  • Modeling, Verification and Pattern Generation for Reconfigurable Scan Networks
    Baranowski, R., Kochte, M.A. and Wunderlich, H.-J.
    Proceedings of the IEEE International Test Conference (ITC'12), Anaheim, California, USA, November 6-8 , pp. 1-9

 


The First International Test Standards Application Workshop (TESTA) Link discusses applications of reconfigurable scan networks and provides an open framework for exchanging ideas especially on the best practices around recently released test standards IEEE 1149.1-2013 and IEEE 1687-2014, as well as IEEE 1500-2005. It takes places on May 26-27, 2016, co-located with the IEEE European Test Symposium in Amsterdam, The Netherlands. The ITI takes part in the workshop organization. 

 

Publications

Journal and Conference Proceedings
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21. Robust Reconfigurable Scan Networks
Lylina, Natalia; Wang, Chih-Hao; Wunderlich, Hans-Joachim
To appear in Proceedings of the Conference on Design, Automation and Test in Europe (DATE'22), Antwerp, Belgium, 14 - 23 March 2022, pp. 1-4
2022
 
Abstract: Reconfigurable Scan Networks (RSNs) access the evaluation results from embedded instruments and control their operation throughout the device lifetime. At the same time, a single fault in an RSN may dramatically reduce the accessibility of the instruments. During post-silicon validation, it may prevent extracting the complete data from a device. During online operation, the inaccessibility of runtime-critical instruments via a defect RSN may eventually result in a system failure. This paper addresses both scenarios above by presenting robust RSNs. We show that by making a small number of carefully selected spots in RSNs more robust, the entire access mechanism becomes significantly more reliable. A flexible cost function assesses the importance of specific control primitives for the overall accessibility of the instruments. Following the cost function, a minimized number of spots is hardened against permanent faults. All the critical instruments as well as most of the remaining instruments remain accessible through the resulting RSNs even in the presence of defects. In contrast to state-of-the-art fault-tolerant RSNs, the presented approach does not change the RSN topology and needs less hardware overhead. Selective hardening is formulated as a multi-objective optimization problem and solved by using an evolutionary algorithm. The experimental results validate the efficiency and the scalability of the approach.
BibTeX:
@inproceedings{LylinWW22,
  author = {Lylina, Natalia and Wang, Chih-Hao and Wunderlich, Hans-Joachim},
  title = {{Robust Reconfigurable Scan Networks}},
  booktitle = {To appear in Proceedings of the Conference on Design, Automation and Test in Europe (DATE'22)},
  year = {2022},
  pages = {1--4},
  abstract = {Reconfigurable Scan Networks (RSNs) access the evaluation results from embedded instruments and control their operation throughout the device lifetime. At the same time, a single fault in an RSN may dramatically reduce the accessibility of the instruments. During post-silicon validation, it may prevent extracting the complete data from a device. During online operation, the inaccessibility of runtime-critical instruments via a defect RSN may eventually result in a system failure. This paper addresses both scenarios above by presenting robust RSNs. We show that by making a small number of carefully selected spots in RSNs more robust, the entire access mechanism becomes significantly more reliable. A flexible cost function assesses the importance of specific control primitives for the overall accessibility of the instruments. Following the cost function, a minimized number of spots is hardened against permanent faults. All the critical instruments as well as most of the remaining instruments remain accessible through the resulting RSNs even in the presence of defects. In contrast to state-of-the-art fault-tolerant RSNs, the presented approach does not change the RSN topology and needs less hardware overhead. Selective hardening is formulated as a multi-objective optimization problem and solved by using an evolutionary algorithm. The experimental results validate the efficiency and the scalability of the approach.}
}
20. SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks
Lylina, Natalia; Wang, Chih-Hao; Wunderlich, Hans-Joachim
To appear in the Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022, pp. 1-14
2022
DOI  
Keywords: Reconfigurable Scan Network, Secure DfT, Design validation, Synthesis, Integer Linear Programming, SAT
Abstract: Reconfigurable Scan Networks (RSNs) enable an efficient reliability management throughout the device lifetime. They can be used for controlling integrated instruments, such as aging monitors or built-in self-test (BIST) registers, as well as for collecting the evaluation results from them. At the same time, they may impose a security threat, since the additional connectivities introduced by the RSN can possibly be misused as a side-channel.
This paper presents an approach for Security Compliance Analysis and Resynthesis (SCAR) of RSNs to integrate an RSN compliant with the security properties of the initial design. First, the reachability properties of the original design are accurately computed. The connectivities inside the RSN, which exceed the allowed connectivity of the initial design, are identified using the presented Security Compliance Analysis. Next, all violations are resolved by automated Resynthesis with a minimized number of structural changes. As a result of SCAR, any information leakage due to the RSN integration is prevented, while the accessibility of the instruments through the RSN is preserved. The approach is able to analyze complex control dependencies and obtains a compliant RSN even for the largest available benchmarks.
BibTeX:
@article{LylinWW22_TCAD,
  author = {Lylina, Natalia and Wang, Chih-Hao and Wunderlich, Hans-Joachim},
  title = {{SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks}},
  journal = {To appear in the Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
  year = {2022},
  pages = {1--14},
  keywords = {Reconfigurable Scan Network, Secure DfT, Design validation, Synthesis, Integer Linear Programming, SAT},
  abstract = {Reconfigurable Scan Networks (RSNs) enable an efficient reliability management throughout the device lifetime. They can be used for controlling integrated instruments, such as aging monitors or built-in self-test (BIST) registers, as well as for collecting the evaluation results from them. At the same time, they may impose a security threat, since the additional connectivities introduced by the RSN can possibly be misused as a side-channel.
This paper presents an approach for Security Compliance Analysis and Resynthesis (SCAR) of RSNs to integrate an RSN compliant with the security properties of the initial design. First, the reachability properties of the original design are accurately computed. The connectivities inside the RSN, which exceed the allowed connectivity of the initial design, are identified using the presented Security Compliance Analysis. Next, all violations are resolved by automated Resynthesis with a minimized number of structural changes. As a result of SCAR, any information leakage due to the RSN integration is prevented, while the accessibility of the instruments through the RSN is preserved. The approach is able to analyze complex control dependencies and obtains a compliant RSN even for the largest available benchmarks.}, doi = {http://dx.doi.org/10.1109/TCAD.2022.3158250} }
19. Testability-Enhancing Resynthesis of Reconfigurable Scan Networks
Lylina, Natalia; Wang, Chih-Hao; Wunderlich, Hans-Joachim
Proceedings of the IEEE International Test Conference (ITC'21), Virtual, 10 - 15 October 2021, pp. 1-10
2021
DOI PDF 
Abstract: Reconfigurable Scan Networks (RSNs) have to be tested before they can be used for post-silicon validation, diagnosis or online reliability management. Even a single stuck-at fault in the switch logic of an RSN can corrupt the scan paths and make instruments inaccessible. Testing the switch logic of an RSN is a complex sequential test problem. The existing test schemes for RSNs rely on the assumption that a fault in the switch logic will be detected by the altered length of the erroneously activated scan path. However, often this assumption does not hold and faults in the switch logic remain undetected. In this paper, an automated testability-enhancing resynthesis is presented. First, the testability of the initial RSN is accurately analyzed. If any single fault in the switch logic is undetectable by the altered path length, a small number of scan cells is inserted into the RSN. The presented scheme is applicable to arbitrary RSN designs and is compliant with state-of-the-art test methods and the applicable standards. The experimental results show the efficacy, the efficiency and the scalability of the approach.
BibTeX:
@inproceedings{LylinWW2021,
  author = {Lylina, Natalia and Wang, Chih-Hao and Wunderlich, Hans-Joachim},
  title = {{Testability-Enhancing Resynthesis of Reconfigurable Scan Networks}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'21)},
  year = {2021},
  pages = {1--10},
  abstract = {Reconfigurable Scan Networks (RSNs) have to be tested before they can be used for post-silicon validation, diagnosis or online reliability management. Even a single stuck-at fault in the switch logic of an RSN can corrupt the scan paths and make instruments inaccessible. Testing the switch logic of an RSN is a complex sequential test problem. The existing test schemes for RSNs rely on the assumption that a fault in the switch logic will be detected by the altered length of the erroneously activated scan path. However, often this assumption does not hold and faults in the switch logic remain undetected. In this paper, an automated testability-enhancing resynthesis is presented. First, the testability of the initial RSN is accurately analyzed. If any single fault in the switch logic is undetectable by the altered path length, a small number of scan cells is inserted into the RSN. The presented scheme is applicable to arbitrary RSN designs and is compliant with state-of-the-art test methods and the applicable standards. The experimental results show the efficacy, the efficiency and the scalability of the approach.},
  doi = {http://dx.doi.org/10.1109/ITC50571.2021.00009},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2021/ITC_LylinWW2021.pdf}
}
18. Concurrent Test of Reconfigurable Scan Networks for Self-Aware Systems
Wang, Chih-Hao; Lylina, Natalia; Atteya, Ahmed; Hsieh, Tong-Yu; Wunderlich, Hans-Joachim
Proceedings of the IEEE International Symposium on On-Line Testing And Robust System Design (IOLTS'21), Virtual, 28-30 June 2021, pp. 1-7
2021
DOI PDF 
Abstract: Self-aware and safety-critical hardware/software systems rely on a variety of embedded instruments, sensors, monitors and design-for-test circuitry to check the system integrity. The access to these internal instruments is supported by standards commonly called iJTAG and employs so called reconfigurable scan networks (RSNs), which are more and more used at runtime, too. They collect periodically and also concurrently the information on the circuit’s health state and deliver it to some dependability management unit. The integrity of RSNs is essential for the dependability of selfaware systems and can be ensured by a combination of periodic and concurrent test methods of the RSN itself. The paper at hand presents the first concurrent online test method for RSNs by adding a brief integrity test to each access operation. The presented scheme includes a hardware extension of negligible size, supports offline test, diagnosis and post-silicon validation as well, and is further referred as ROSTI : RSN Online/Offline SelfTest Infrastructure. It exploits the original RSN control signals and does not require any modification of the underlying RSN. The hardware costs are independent of the size of the RSN, and ROSTI is flexible for generating different test sequences for different types of faults. The experimental results validate these characteristics and show that ROSTI is highly scalable.
BibTeX:
@inproceedings{WangALW21,
  author = {Wang, Chih-Hao and Lylina, Natalia and Atteya, Ahmed and Hsieh, Tong-Yu and Wunderlich, Hans-Joachim},
  title = {{Concurrent Test of Reconfigurable Scan Networks for Self-Aware Systems}},
  booktitle = {Proceedings of the IEEE International Symposium on On-Line Testing And Robust System Design (IOLTS'21)},
  year = {2021},
  pages = {1--7},
  abstract = {Self-aware and safety-critical hardware/software systems rely on a variety of embedded instruments, sensors, monitors and design-for-test circuitry to check the system integrity. The access to these internal instruments is supported by standards commonly called iJTAG and employs so called reconfigurable scan networks (RSNs), which are more and more used at runtime, too. They collect periodically and also concurrently the information on the circuit’s health state and deliver it to some dependability management unit. The integrity of RSNs is essential for the dependability of selfaware systems and can be ensured by a combination of periodic and concurrent test methods of the RSN itself. The paper at hand presents the first concurrent online test method for RSNs by adding a brief integrity test to each access operation. The presented scheme includes a hardware extension of negligible size, supports offline test, diagnosis and post-silicon validation as well, and is further referred as ROSTI : RSN Online/Offline SelfTest Infrastructure. It exploits the original RSN control signals and does not require any modification of the underlying RSN. The hardware costs are independent of the size of the RSN, and ROSTI is flexible for generating different test sequences for different types of faults. The experimental results validate these characteristics and show that ROSTI is highly scalable.},
  doi = {http://dx.doi.org/10.1109/IOLTS52814.2021.9486710},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2021/IOLTS_WangLAHW2021.pdf}
}
17. A Hybrid Protection Scheme for Reconfigurable Scan Networks
Lylina, Natalia; Atteya, Ahmed; Wunderlich, Hans-Joachim
Proceedings of the IEEE VLSI Test Symposium (VTS'21), Virtual, 25-28 April 2021, pp. 1-7
2021
DOI PDF 
Abstract: The reliable operation of integrated systems is supported by Reconfigurable Scan Networks (RSNs) which allow to access efficiently the embedded instruments throughout the life-cycle. However, the RSN integration may introduce additional connectivities into a Device-under-Test (DUT), and the RSN might be misused for information leakage. Structural methods resynthesize the RSNs and add hardware components such that certain instruments are physically separated, while functional approaches add filters to prevent certain access patterns. Both methods have certain limitations. This paper presents an effective approach to maximize the benefits and to overcome the limitations of the existing solutions by a hybrid combination of structural and functional protection schemes. A minimized number of structural changes is identified in order to resolve violations which cannot be handled by using sequence filters. The remaining violations are resolved functionally by using filters and a flexible protection can be enabled for multiple user groups with different access permissions. Since the majority of the violations are resolved using a filter, the hardware overhead for structural changes is drastically reduced. The efficiency of the approach is supported by experimental results.
BibTeX:
@inproceedings{LylinAW2021,
  author = {Lylina, Natalia and Atteya, Ahmed and Wunderlich, Hans-Joachim},
  title = {{A Hybrid Protection Scheme for Reconfigurable Scan Networks}},
  booktitle = {Proceedings of the IEEE VLSI Test Symposium (VTS'21)},
  year = {2021},
  pages = {1--7},
  abstract = {The reliable operation of integrated systems is supported by Reconfigurable Scan Networks (RSNs) which allow to access efficiently the embedded instruments throughout the life-cycle. However, the RSN integration may introduce additional connectivities into a Device-under-Test (DUT), and the RSN might be misused for information leakage. Structural methods resynthesize the RSNs and add hardware components such that certain instruments are physically separated, while functional approaches add filters to prevent certain access patterns. Both methods have certain limitations. This paper presents an effective approach to maximize the benefits and to overcome the limitations of the existing solutions by a hybrid combination of structural and functional protection schemes. A minimized number of structural changes is identified in order to resolve violations which cannot be handled by using sequence filters. The remaining violations are resolved functionally by using filters and a flexible protection can be enabled for multiple user groups with different access permissions. Since the majority of the violations are resolved using a filter, the hardware overhead for structural changes is drastically reduced. The efficiency of the approach is supported by experimental results. },
  doi = {http://dx.doi.org/10.1109/VTS50974.2021.9441029},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2021/VTS_LylinAW2021.pdf}
}
16. Security Preserving Integration and Re-Synthesis of Reconfigurable Scan Networks
Lylina, Natalia; Atteya, Ahmed; Wang, Chih-Hao; Wunderlich, Hans-Joachim
Proceedings of the IEEE International Test Conference (ITC'20), 1-6 November 2020
2020
DOI PDF 
Abstract: Reliable operation, test, debug and diagnosis of complex integrated systems are ensured by embedded instruments, such as sensors, aging monitors or Built-In Self-Test (BIST) registers. Reconfigurable Scan Networks (RSNs) offer a flexible and efficient way to access such test instruments throughout the whole life-cycle. However, improper RSN integration might introduce additional connectivity properties to the device under test (DUT), which can be exploited to perform unauthorized access or cause information leakage. The existence of such additional connectivity through the RSN can compromise the security of the DUT and is considered as a security threat.In this paper, a method is presented to resolve all such security compliance violations. The problem is formulated in terms of Integer Linear Programming (ILP) as a minimum cut problem in multicommodity flow. An efficient heuristic is presented, which, to our knowledge, for the first time allows to consider the whole set of violations simultaneously and thereby to find a minimized number of changes to the RSN structure in order to make it compliant with the initial security requirements of the DUT and prevent the information leakage through the scan chain.
BibTeX:
@inproceedings{Lylin2020AWW,
  author = {Lylina, Natalia and Atteya, Ahmed and Wang, Chih-Hao and Wunderlich, Hans-Joachim},
  title = {{Security Preserving Integration and Re-Synthesis of Reconfigurable Scan Networks}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'20)},
  year = {2020},
  abstract = {Reliable operation, test, debug and diagnosis of complex integrated systems are ensured by embedded instruments, such as sensors, aging monitors or Built-In Self-Test (BIST) registers. Reconfigurable Scan Networks (RSNs) offer a flexible and efficient way to access such test instruments throughout the whole life-cycle. However, improper RSN integration might introduce additional connectivity properties to the device under test (DUT), which can be exploited to perform unauthorized access or cause information leakage. The existence of such additional connectivity through the RSN can compromise the security of the DUT and is considered as a security threat.In this paper, a method is presented to resolve all such security compliance violations. The problem is formulated in terms of Integer Linear Programming (ILP) as a minimum cut problem in multicommodity flow. An efficient heuristic is presented, which, to our knowledge, for the first time allows to consider the whole set of violations simultaneously and thereby to find a minimized number of changes to the RSN structure in order to make it compliant with the initial security requirements of the DUT and prevent the information leakage through the scan chain.},
  doi = {http://dx.doi.org/10.1109/ITC44778.2020.9325227},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2020/ITC_LylinAWW2020.pdf}
}
15. Synthesis of Fault-Tolerant Reconfigurable Scan Networks
Brandhofer, Sebastian; Kochte, Michael A.; Wunderlich, Hans-Joachim
Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'20), Grenoble, France, 9-13 March 2020, pp. 1-6
2020
DOI PDF 
Abstract: On-chip instrumentation is mandatory for efficient bring-up, test and diagnosis, post-silicon validation, as well as in-field calibration, maintenance, and fault tolerance. Reconfigurable scan networks (RSNs) provide a scalable and efficient scan-based access mechanism to such instruments. The correct operation of this access mechanism is crucial for all manufacturing, bring-up and debug tasks as well as for in-field operation, but it can be affected by faults and design errors. This work develops for the first time fault-tolerant RSNs such that the resulting scan network still provides access to as many instruments as possible in presence of a fault. The work contributes a model and an algorithm to compute scan paths in faulty RSNs, a metric to quantify its fault tolerance and a synthesis algorithm that is based on graph connectivity and selective hardening of control logic in the scan network. Experimental results demonstrate that fault-tolerant RSNs can be synthesized with only moderate hardware overhead.
BibTeX:
@inproceedings{BrandKW2020,
  author = {Brandhofer, Sebastian and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Synthesis of Fault-Tolerant Reconfigurable Scan Networks}},
  booktitle = {Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'20)},
  year = {2020},
  pages = {1--6},
  abstract = {On-chip instrumentation is mandatory for efficient bring-up, test and diagnosis, post-silicon validation, as well as in-field calibration, maintenance, and fault tolerance. Reconfigurable scan networks (RSNs) provide a scalable and efficient scan-based access mechanism to such instruments. The correct operation of this access mechanism is crucial for all manufacturing, bring-up and debug tasks as well as for in-field operation, but it can be affected by faults and design errors. This work develops for the first time fault-tolerant RSNs such that the resulting scan network still provides access to as many instruments as possible in presence of a fault. The work contributes a model and an algorithm to compute scan paths in faulty RSNs, a metric to quantify its fault tolerance and a synthesis algorithm that is based on graph connectivity and selective hardening of control logic in the scan network. Experimental results demonstrate that fault-tolerant RSNs can be synthesized with only moderate hardware overhead.},
  doi = {http://dx.doi.org/10.23919/DATE48585.2020.9116525},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2020/DATE_BrandKW2020.pdf}
}
14. SWIFT: Switch Level Fault Simulation on GPUs
Schneider, Eric; Wunderlich, Hans-Joachim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Vol. 38(1), January 2019, pp. 122-135
2019
DOI PDF 
Keywords: parallel simulation, fault simulation, switch level, parametric faults, complex gates, variation analysis, GPU
Abstract: Current nanometer CMOS circuits show an increasing sensitivity to deviations in first-order parameters and suffer from process variations during manufacturing. To properly assess and support test validation of digital designs, low-level fault simulation approaches are utilized to accurately capture the behavior of CMOS cells under parametric faults and process variations as early as possible throughout the design phase. However, low-level simulation approaches exhibit a high computational complexity, especially when variation has to be taken into account. In this work a high-throughput parallel fault simulation at switch level is presented. First-order electrical parameters are utilized to capture CMOS-specific functional and timing behavior of complex cells allowing to model faults with transistor granularity and without the need of logic abstraction. Furthermore, variation modeling in cells and transistor devices enables broad and efficient variation analyses of faults over many circuit instances for the first time. The simulation approach utilizes massive parallelization on Graphics Processing Units (GPUs) by exploiting parallelism from cells, stimuli, faults and circuit instances. Despite the lower abstraction levels of the approach, it processes designs with millions of gates and outperforms conventional fault simulation at logic level in terms of speed and accuracy.
BibTeX:
@article{SchneW2018,
  author = {Schneider, Eric and Wunderlich, Hans-Joachim},
  title = {{SWIFT: Switch Level Fault Simulation on GPUs}},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
  year = {2019},
  volume = {38},
  number = {1},
  pages = {122--135},
  keywords = {parallel simulation, fault simulation, switch level, parametric faults, complex gates, variation analysis, GPU},
  abstract = {Current nanometer CMOS circuits show an increasing sensitivity to deviations in first-order parameters and suffer from process variations during manufacturing. To properly assess and support test validation of digital designs, low-level fault simulation approaches are utilized to accurately capture the behavior of CMOS cells under parametric faults and process variations as early as possible throughout the design phase. However, low-level simulation approaches exhibit a high computational complexity, especially when variation has to be taken into account. In this work a high-throughput parallel fault simulation at switch level is presented. First-order electrical parameters are utilized to capture CMOS-specific functional and timing behavior of complex cells allowing to model faults with transistor granularity and without the need of logic abstraction. Furthermore, variation modeling in cells and transistor devices enables broad and efficient variation analyses of faults over many circuit instances for the first time. The simulation approach utilizes massive parallelization on Graphics Processing Units (GPUs) by exploiting parallelism from cells, stimuli, faults and circuit instances. Despite the lower abstraction levels of the approach, it processes designs with millions of gates and outperforms conventional fault simulation at logic level in terms of speed and accuracy.},
  doi = {http://dx.doi.org/10.1109/TCAD.2018.2802871},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2018/TCAD_SchneW2018.pdf}
}
13. Self-Test and Diagnosis for Self-Aware Systems
Kochte, Michael A.; Wunderlich, Hans-Joachim
IEEE Design & Test
Vol. 35(5), 13 October 2018, pp. 7-18
2018
DOI PDF 
Keywords: Self-test, diagnosis, health monitoring, fault management, on-chip infrastructure
Abstract: Self-awareness allows autonomous systems the dynamic adaptation to changing states of the hardware platform and the optimal usage of available computing resources. This demands concurrent, periodical, or on-demand monitoring and testing of the hardware structures to detect and classify deviations from the nominal behavior and appropriate reactions. This survey discusses suitable self-test, self-checking, and self-diagnosis methods for the realization of self-awareness and presents two case studies in which such methods are applied at different levels.
BibTeX:
@article{KochtW2017,
  author = {Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Self-Test and Diagnosis for Self-Aware Systems}},
  journal = {IEEE Design & Test},
  year = {2018},
  volume = {35},
  number = {5},
  pages = {7--18},
  keywords = {Self-test, diagnosis, health monitoring, fault management, on-chip infrastructure},
  abstract = {Self-awareness allows autonomous systems the dynamic adaptation to changing states of the hardware platform and the optimal usage of available computing resources. This demands concurrent, periodical, or on-demand monitoring and testing of the hardware structures to detect and classify deviations from the nominal behavior and appropriate reactions. This survey discusses suitable self-test, self-checking, and self-diagnosis methods for the realization of self-awareness and presents two case studies in which such methods are applied at different levels.},
  doi = {http://dx.doi.org/10.1109/MDAT.2017.2762903},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2017/DT_KochtW2017.pdf}
}
12. Multi-Level Timing Simulation on GPUs
Schneider, Eric; Kochte, Michael A.; Wunderlich, Hans-Joachim
Proceedings of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC'18), Jeju Island, Korea, 22-25 January 2018 , pp. 470-475
2018
DOI PDF 
Keywords: timing simulation, switch level, multi-level, parallel simulation, GPUs
Abstract: Timing-accurate simulation of circuits is an important task in design validation of modern nano-scale CMOS circuits. With shrinking technology nodes, detailed simulation models down to transistor level have to be considered. While conventional simulation at logic level lacks the ability to accurately model timing behavior for complex cells, more accurate simulation at lower abstraction levels becomes computationally expensive for larger designs. This work presents the first parallel multi-level waveform-accurate timing simulation approach on graphics processing units (GPUs). The simulation uses logic and switch level abstraction concurrently, thus allowing to combine their advantages by trading off speed and accuracy. The abstraction can be lowered in arbitrary regions of interest to locally increase the accuracy. Waveform transformations allow for transparent switching between the abstraction levels. With the utilization of GPUs and thoughtful unification of algorithms and data structures, a fast and versatile high-throughput multi-level simulation is obtained that is scalable for millions of cells while achieving runtime savings of up to 89% compared to full simulation at switch level.
BibTeX:
@inproceedings{SchneKW2018,
  author = {Schneider, Eric and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Multi-Level Timing Simulation on GPUs}},
  booktitle = {Proceedings of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC'18)},
  year = { 2018 },
  pages = {470--475},
  keywords = {timing simulation, switch level, multi-level, parallel simulation, GPUs},
  abstract = {Timing-accurate simulation of circuits is an important task in design validation of modern nano-scale CMOS circuits. With shrinking technology nodes, detailed simulation models down to transistor level have to be considered. While conventional simulation at logic level lacks the ability to accurately model timing behavior for complex cells, more accurate simulation at lower abstraction levels becomes computationally expensive for larger designs. This work presents the first parallel multi-level waveform-accurate timing simulation approach on graphics processing units (GPUs). The simulation uses logic and switch level abstraction concurrently, thus allowing to combine their advantages by trading off speed and accuracy. The abstraction can be lowered in arbitrary regions of interest to locally increase the accuracy. Waveform transformations allow for transparent switching between the abstraction levels. With the utilization of GPUs and thoughtful unification of algorithms and data structures, a fast and versatile high-throughput multi-level simulation is obtained that is scalable for millions of cells while achieving runtime savings of up to 89% compared to full simulation at switch level.},
  doi = {http://dx.doi.org/10.1109/ASPDAC.2018.8297368},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2018/ASPDAC_SchneKW2018.pdf}
}
11. Structure-oriented Test of Reconfigurable Scan Networks
Ull, Dominik; Kochte, Michael A.; Wunderlich, Hans-Joachim
Proceedings of the 26th IEEE Asian Test Symposium (ATS'17), Taipei, Taiwan, 27-30 November 2017
2017
DOI PDF 
Keywords: Design-for-test, test generation, reconfigurable scan network, on-chip infrastructure, IEEE Std. 1687, iJTAG
Abstract: Design, production and operation of modern system-on-chips rely on integrated instruments, which range from simple sensors to complex debug interfaces and design-for-test (DfT) structures. Reconfigurable scan networks (RSNs) as defined in IEEE Std. 1687-2014 provide an efficient access mechanism to such instruments. It is essential to test the access mechanism itself before it can be used for test, diagnosis, validation, calibration or runtime monitoring. Realistic fault mechanisms in RSNs are hard to test due to their high sequential depth and limited controllability and observability via serial scan ports. We present a novel low-cost DfT modification specifically designed for RSNs that enhances the observability of shadow registers. Furthermore, we present different test methods for stuck-at and more realistic gate-level fault models like flip-flop- internal and bridge faults. Experimental results demonstrate the effectiveness of the presented DfT modification and test methods.
BibTeX:
@inproceedings{UllKW2017,
  author = {Ull, Dominik and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Structure-oriented Test of Reconfigurable Scan Networks}},
  booktitle = {Proceedings of the 26th IEEE Asian Test Symposium (ATS'17)},
  year = {2017},
  keywords = {Design-for-test, test generation, reconfigurable scan network, on-chip infrastructure, IEEE Std. 1687, iJTAG},
  abstract = {Design, production and operation of modern system-on-chips rely on integrated instruments, which range from simple sensors to complex debug interfaces and design-for-test (DfT) structures. Reconfigurable scan networks (RSNs) as defined in IEEE Std. 1687-2014 provide an efficient access mechanism to such instruments. It is essential to test the access mechanism itself before it can be used for test, diagnosis, validation, calibration or runtime monitoring. Realistic fault mechanisms in RSNs are hard to test due to their high sequential depth and limited controllability and observability via serial scan ports. We present a novel low-cost DfT modification specifically designed for RSNs that enhances the observability of shadow registers. Furthermore, we present different test methods for stuck-at and more realistic gate-level fault models like flip-flop- internal and bridge faults. Experimental results demonstrate the effectiveness of the presented DfT modification and test methods.},
  doi = {http://dx.doi.org/10.1109/ATS.2017.34},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2017/ATS_UllKW2017.pdf}
}
10. Test Strategies for Reconfigurable Scan Networks
Kochte, Michael A.; Baranowski, Rafal; Schaal, Marcel; Wunderlich, Hans-Joachim
Proceedings of the 25th IEEE Asian Test Symposium (ATS'16), Hiroshima, Japan, 21-24 November 2016, pp. 113-118
2016
DOI PDF 
Keywords: Test generation, reconfigurable scan network, design-for-test, on-chip infrastructure, IEEE Std 1687, iJTAG
Abstract: On-chip infrastructure is an essential part of today’s complex designs and enables their cost-efficient manufacturing and operation. The diversity and high number of infrastructure elements demands flexible and low-latency access mechanisms, such as reconfigurable scan networks (RSNs). The correct operation of the infrastructure access itself is highly important for the test of the system logic, its diagnosis, debug and bring-up, as well as post-silicon validation. Ensuring correct operation requires the thorough testing of the RSN. Because of sequential and combinational dependencies in RSN accesses, test generation for general RSNs is computationally very difficult and requires dedicated test strategies. This paper explores different test strategies for general RSNs and discusses the achieved structural fault coverage. Experimental results show that the combination of functional test heuristics together with a dedicated RSN test pattern generation approach significantly outperforms the test quality of a standard ATPG tool.
BibTeX:
@inproceedings{KochtBSW2016,
  author = {Kochte, Michael A. and Baranowski, Rafal and Schaal, Marcel and Wunderlich, Hans-Joachim},
  title = {{Test Strategies for Reconfigurable Scan Networks}},
  booktitle = {Proceedings of the 25th IEEE Asian Test Symposium (ATS'16)},
  year = {2016},
  pages = {113--118},
  keywords = {Test generation, reconfigurable scan network, design-for-test, on-chip infrastructure, IEEE Std 1687, iJTAG},
  abstract = {On-chip infrastructure is an essential part of today’s complex designs and enables their cost-efficient manufacturing and operation. The diversity and high number of infrastructure elements demands flexible and low-latency access mechanisms, such as reconfigurable scan networks (RSNs). The correct operation of the infrastructure access itself is highly important for the test of the system logic, its diagnosis, debug and bring-up, as well as post-silicon validation. Ensuring correct operation requires the thorough testing of the RSN. Because of sequential and combinational dependencies in RSN accesses, test generation for general RSNs is computationally very difficult and requires dedicated test strategies. This paper explores different test strategies for general RSNs and discusses the achieved structural fault coverage. Experimental results show that the combination of functional test heuristics together with a dedicated RSN test pattern generation approach significantly outperforms the test quality of a standard ATPG tool.},
  doi = {http://dx.doi.org/10.1109/ATS.2016.35},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/ATS_KochtBSW2016.pdf}
}
9. Autonomous Testing for 3D-ICs with IEEE Std. 1687
Ye, Jin-Cun; Kochte, Michael A.; Lee, Kuen-Jong; Wunderlich, Hans-Joachim
Proceedings of the 25th IEEE Asian Test Symposium (ATS'16), Hiroshima, Japan, 21-24 November 2016, pp. 215-220
2016
DOI PDF 
Keywords: IEEE Std. 1687, IJTAG, reconfigurable scan network, autonomous testing, 3D-ICs, DFT
Abstract: IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing embedded instruments efficiently. In this paper, we present a novel test architecture that employs IEEE Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test controller can deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and provide required control signals to control the whole test procedure. This design can achieve at-speed, autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area and test cycle overhead of this architecture is small considering its autonomous test capability.
BibTeX:
@inproceedings{YeKLW2016,
  author = {Ye, Jin-Cun and Kochte, Michael A. and Lee, Kuen-Jong and Wunderlich, Hans-Joachim},
  title = {{Autonomous Testing for 3D-ICs with IEEE Std. 1687}},
  booktitle = {Proceedings of the 25th IEEE Asian Test Symposium (ATS'16)},
  year = {2016},
  pages = {215--220},
  keywords = {IEEE Std. 1687, IJTAG, reconfigurable scan network, autonomous testing, 3D-ICs, DFT},
  abstract = {IEEE Std. 1687, or IJTAG, defines flexible serial scan-based architectures for accessing embedded instruments efficiently. In this paper, we present a novel test architecture that employs IEEE Std. 1687 together with an efficient test controller to carry out 3D-IC testing autonomously. The test controller can deliver parallel test data for the IEEE Std. 1687 structures and the cores under test, and provide required control signals to control the whole test procedure. This design can achieve at-speed, autonomous and programmable testing in 3D-ICs. Experimental results show that the additional area and test cycle overhead of this architecture is small considering its autonomous test capability.},
  doi = {http://dx.doi.org/10.1109/ATS.2016.56},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/ATS_YeKLW2016.pdf}
}
8. Formal Verification of Secure Reconfigurable Scan Network Infrastructure
Kochte, Michael A.; Baranowski, Rafal; Sauer, Matthias; Becker, Bernd; Wunderlich, Hans-Joachim
Proceedings of the 21st IEEE European Test Symposium (ETS'16), Amsterdam, The Netherlands, 23-27 May 2016 , pp. 1-6
2016
DOI PDF 
Keywords: Security, Formal verification, IEEE Std 1687, IJTAG, Reconfigurable scan network, Infrastructure, Sidechannel attack
Abstract: Reconfigurable scan networks (RSN) as standardized by IEEE Std 1687 allow flexible and efficient access to on-chip infrastructure for test and diagnosis, post-silicon validation, debug, bring-up, or maintenance in the field. However, unauthorized access or manipulation of the attached instruments, monitors, or controllers pose security and safety risks. Different RSN architectures have recently been proposed to implement secure access to the connected instruments, for instance by authentication and authorization. To ensure that the implemented security schemes cannot be bypassed, design verification of the security properties is mandatory. However, combinational and deep sequential dependencies of modern RSNs and their extensions for security require novel approaches to formal verification for unbounded model checking. This work presents for the first time a formal design verification methodology for security properties of RSNs based on unbounded model checking that is able to verify access protection at logical level. Experimental results demonstrate that state-of-the-art security schemes for RSNs can be efficiently handled, even for very large designs.
BibTeX:
@inproceedings{KochtBSBW2016,
  author = {Kochte, Michael A. and Baranowski, Rafal and Sauer, Matthias and Becker, Bernd and Wunderlich, Hans-Joachim },
  title = {{Formal Verification of Secure Reconfigurable Scan Network Infrastructure}},
  booktitle = {Proceedings of the 21st IEEE European Test Symposium (ETS'16)},
  year = { 2016 },
  pages = {1-6},
  keywords = {Security, Formal verification, IEEE Std 1687, IJTAG, Reconfigurable scan network, Infrastructure, Sidechannel attack},
  abstract = {Reconfigurable scan networks (RSN) as standardized by IEEE Std 1687 allow flexible and efficient access to on-chip infrastructure for test and diagnosis, post-silicon validation, debug, bring-up, or maintenance in the field. However, unauthorized access or manipulation of the attached instruments, monitors, or controllers pose security and safety risks. Different RSN architectures have recently been proposed to implement secure access to the connected instruments, for instance by authentication and authorization. To ensure that the implemented security schemes cannot be bypassed, design verification of the security properties is mandatory. However, combinational and deep sequential dependencies of modern RSNs and their extensions for security require novel approaches to formal verification for unbounded model checking. This work presents for the first time a formal design verification methodology for security properties of RSNs based on unbounded model checking that is able to verify access protection at logical level. Experimental results demonstrate that state-of-the-art security schemes for RSNs can be efficiently handled, even for very large designs.},
  doi = {http://dx.doi.org/10.1109/ETS.2016.7519290},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/ETS_KochtBSBW2016.pdf}
}
7. Dependable On-Chip Infrastructure for Dependable MPSOCs
Kochte, Michael A.; Wunderlich, Hans-Joachim
Proceedings of the 17th IEEE Latin American Test Symposium (LATS'16), Foz do Iguaçu, Brazil, 6-8 April 2016 , pp. 183-188
2016
DOI PDF 
Keywords: Dependability, on-chip infrastructure, reconfigurable scan network, IEEE Std 1687, iJTAG, hardware security
Abstract: Today's MPSOCs employ complex on-chip infrastructure and instrumentation for efficient test, debug, diagnosis, and post-silicon validation, reliability management and maintenance in the field, or monitoring and calibration during operation. To enable flexible and efficient access to such instrumentation, reconfigurable scan networks (RSNs) as recently standardized by IEEE Std 1687 can be used. Given the importance of infrastructure for the dependability of the whole MPSOC, however, the RSN itself must be highly dependable. This paper addresses dependability issues of RSNs including verification, test, and security, and their importance for dependable MPSOCs. First research results are summarized, and open questions for future work are highlighted.
BibTeX:
@inproceedings{KochtW2016,
  author = {Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Dependable On-Chip Infrastructure for Dependable MPSOCs}},
  booktitle = {Proceedings of the 17th IEEE Latin American Test Symposium (LATS'16)},
  year = { 2016 },
  pages = {183-188},
  keywords = { Dependability, on-chip infrastructure, reconfigurable scan network, IEEE Std 1687, iJTAG, hardware security },
  abstract = {Today's MPSOCs employ complex on-chip infrastructure and instrumentation for efficient test, debug, diagnosis, and post-silicon validation, reliability management and maintenance in the field, or monitoring and calibration during operation. To enable flexible and efficient access to such instrumentation, reconfigurable scan networks (RSNs) as recently standardized by IEEE Std 1687 can be used. Given the importance of infrastructure for the dependability of the whole MPSOC, however, the RSN itself must be highly dependable. This paper addresses dependability issues of RSNs including verification, test, and security, and their importance for dependable MPSOCs. First research results are summarized, and open questions for future work are highlighted.},
  doi = {http://dx.doi.org/10.1109/LATW.2016.7483366},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/LATS_KochtW2016.pdf}
}
6. Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns
Erb, Dominik; Scheibler, Karsten; Kochte, Michael A.; Sauer, Matthias; Wunderlich, Hans-Joachim; Becker, Bernd
Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC'16), Macao SAR, China, 25-28 January 2016 , pp. 749-754
2016
DOI PDF 
Keywords: Unknown values, test generation, Restricted symbolic logic, SAT, Stuck-at fault
Abstract: Unknown (X) values in a design introduce pessimism in conventional test generation algorithms which results in a loss of fault coverage. This pessimism is reduced by a more accurate modeling and analysis. Unfortunately, accurate analysis techniques highly increase runtime and limit scalability. One promising technique to prevent high runtimes while still providing high accuracy is the use of restricted symbolic logic (RSL). However, also pure RSL-based algorithms reach their limits as soon as millon gate circuits need to be processed. In this paper, we propose new ATPG techniques to overcome such limitations. An efficient hybrid encoding combines the accuracy of RSL-based modeling with the compactness of conventional threevalued encoding. A low-cost two-valued SAT-based untestability check is able to classify most untestable faults with low runtime. An incremental and event-based accurate fault simulator is introduced to reduce fault simulation effort. The experiments demonstrate the effectiveness of the proposed techniques. Over 97% of the faults are accurately classified. Both the number of aborts and the total runtime are significantly reduced compared to the state-of-the-art pure RSL-based algorithm. For circuits up to a million gates, the fault coverage could be increased considerably compared to a state-of-the-art commercial tool with very competitive runtimes.
BibTeX:
@inproceedings{ErbSKSWB2016,
  author = {Erb, Dominik and Scheibler, Karsten and Kochte, Michael A. and Sauer, Matthias and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns}},
  booktitle = {Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC'16)},
  year = { 2016 },
  pages = {749-754},
  keywords = {Unknown values, test generation, Restricted symbolic logic, SAT, Stuck-at fault},
  abstract = {Unknown (X) values in a design introduce pessimism in conventional test generation algorithms which results in a loss of fault coverage. This pessimism is reduced by a more accurate modeling and analysis. Unfortunately, accurate analysis techniques highly increase runtime and limit scalability. One promising technique to prevent high runtimes while still providing high accuracy is the use of restricted symbolic logic (RSL). However, also pure RSL-based algorithms reach their limits as soon as millon gate circuits need to be processed. In this paper, we propose new ATPG techniques to overcome such limitations. An efficient hybrid encoding combines the accuracy of RSL-based modeling with the compactness of conventional threevalued encoding. A low-cost two-valued SAT-based untestability check is able to classify most untestable faults with low runtime. An incremental and event-based accurate fault simulator is introduced to reduce fault simulation effort. The experiments demonstrate the effectiveness of the proposed techniques. Over 97% of the faults are accurately classified. Both the number of aborts and the total runtime are significantly reduced compared to the state-of-the-art pure RSL-based algorithm. For circuits up to a million gates, the fault coverage could be increased considerably compared to a state-of-the-art commercial tool with very competitive runtimes.},
  doi = {http://dx.doi.org/10.1109/ASPDAC.2016.7428101},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2016/ASPDAC_ErbSKSWB2016.pdf}
}
5. Accurate QBF-based Test Pattern Generation in Presence of Unknown Values
Erb, Dominik; Kochte, Michael A.; Reimer, Sven; Sauer, Matthias; Wunderlich, Hans-Joachim; Becker, Bernd
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Vol. 34(12), December 2015, pp. 2025-2038
2015
DOI PDF 
Keywords: Unknown values, X-values, ATPG, QBF, SAT, stuck-at fault, transition-delay fault
Abstract: Unknown (X) values emerge during the design process as well as during system operation and test application. X-sources are for instance black boxes in design models, clockdomain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements. To compute a test pattern for a given fault, well-defined logic values are required both for fault activation and propagation to observing outputs. In presence of X-values, conventional test generation algorithms, based on structural algorithms, Boolean satisfiability (SAT), or BDD-based reasoning may fail to generate test patterns or to prove faults untestable. This work proposes the first efficient stuck-at and transitiondelay fault test generation algorithm able to prove testability or untestability of faults in presence of X-values. It overcomes the principal pessimism of conventional algorithms when X-values are considered by mapping the test generation problem to the satisfiability of Quantified Boolean Formulae (QBF). Experiments on ISCAS benchmarks and larger industrial circuits investigate the increase in fault coverage for conventional deterministic and potential detection requirements for both randomized and clustered X-sources.
BibTeX:
@article{ErbKRSWB2015,
  author = {Erb, Dominik and Kochte, Michael A. and Reimer, Sven and Sauer, Matthias and Wunderlich, Hans-Joachim and Becker, Bernd},
  title = {{Accurate QBF-based Test Pattern Generation in Presence of Unknown Values}},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
  year = {2015},
  volume = {34},
  number = {12},
  pages = {2025--2038},
  keywords = {Unknown values, X-values, ATPG, QBF, SAT, stuck-at fault, transition-delay fault},
  abstract = { Unknown (X) values emerge during the design process as well as during system operation and test application. X-sources are for instance black boxes in design models, clockdomain boundaries, analog-to-digital converters, or uncontrolled or uninitialized sequential elements. To compute a test pattern for a given fault, well-defined logic values are required both for fault activation and propagation to observing outputs. In presence of X-values, conventional test generation algorithms, based on structural algorithms, Boolean satisfiability (SAT), or BDD-based reasoning may fail to generate test patterns or to prove faults untestable. This work proposes the first efficient stuck-at and transitiondelay fault test generation algorithm able to prove testability or untestability of faults in presence of X-values. It overcomes the principal pessimism of conventional algorithms when X-values are considered by mapping the test generation problem to the satisfiability of Quantified Boolean Formulae (QBF). Experiments on ISCAS benchmarks and larger industrial circuits investigate the increase in fault coverage for conventional deterministic and potential detection requirements for both randomized and clustered X-sources.},
  doi = {http://dx.doi.org/10.1109/TCAD.2015.2440315},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/TCAD_ErbKRSWB2015.pdf}
}
4. Fine-Grained Access Management in Reconfigurable Scan Networks
Baranowski, Rafal; Kochte, Michael A.; Wunderlich, Hans-Joachim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Vol. 34(6), June 2015, pp. 937-946
2015
DOI PDF 
Keywords: Debug and diagnosis, reconfigurable scan network, IJTAG, IEEE Std 1687, secure DFT, hardware security, instrument protection
Abstract: Modern VLSI designs incorporate a high amount of instrumentation that supports post-silicon validation and debug, volume test and diagnosis, as well as in-field system monitoring and maintenance. Reconfigurable scan architectures, as allowed by the novel IEEE Std 1149.1-2013 (JTAG) and IEEE Std 1687- 2014 (IJTAG), emerge as a scalable mechanism for access to such on-chip instruments. While the on-chip instrumentation is crucial for meeting quality, dependability, and time-to-market goals, it is prone to abuse and threatens system safety and security. A secure access management method is mandatory to assure that critical instruments be accessible to authorized entities only. This work presents a novel protection method for fine-grained access management in complex reconfigurable scan networks based on a challenge-response authentication protocol. The target scan network is extended with an authorization instrument and Secure Segment Insertion Bits (S²IB) that together control the accessibility of individual instruments. To the best of the authors’ knowledge, this is the first fine-grained access management scheme that scales well with the number of protected instruments and offers a high level of security. Compared with recent stateof- the-art techniques, this scheme is more favorable with respect to implementation cost, performance overhead, and provided security level.
BibTeX:
@article{BaranKW2015a,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Fine-Grained Access Management in Reconfigurable Scan Networks}},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
  year = {2015},
  volume = {34},
  number = {6},
  pages = {937--946},
  keywords = {Debug and diagnosis, reconfigurable scan network, IJTAG, IEEE Std 1687, secure DFT, hardware security, instrument protection},
  abstract = {Modern VLSI designs incorporate a high amount of instrumentation that supports post-silicon validation and debug, volume test and diagnosis, as well as in-field system monitoring and maintenance. Reconfigurable scan architectures, as allowed by the novel IEEE Std 1149.1-2013 (JTAG) and IEEE Std 1687- 2014 (IJTAG), emerge as a scalable mechanism for access to such on-chip instruments. While the on-chip instrumentation is crucial for meeting quality, dependability, and time-to-market goals, it is prone to abuse and threatens system safety and security. A secure access management method is mandatory to assure that critical instruments be accessible to authorized entities only. This work presents a novel protection method for fine-grained access management in complex reconfigurable scan networks based on a challenge-response authentication protocol. The target scan network is extended with an authorization instrument and Secure Segment Insertion Bits (S²IB) that together control the accessibility of individual instruments. To the best of the authors’ knowledge, this is the first fine-grained access management scheme that scales well with the number of protected instruments and offers a high level of security. Compared with recent stateof- the-art techniques, this scheme is more favorable with respect to implementation cost, performance overhead, and provided security level.},
  doi = {http://dx.doi.org/10.1109/TCAD.2015.2391266},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/TCAD_BaranKW2015.pdf}
}
3. Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation
Baranowski, Rafal; Kochte, Michael A.; Wunderlich, Hans-Joachim
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Vol. 20(2), February 2015, pp. 30:1-30:27
2015
DOI PDF 
Keywords: Algorithms, Verification, Performance
Abstract: Efficient access to on-chip instrumentation is a key requirement for post-silicon validation, test, debug, bringup, and diagnosis. Reconfigurable scan networks, as proposed by e.g. IEEE P1687 and IEEE Std 1149.1-2013, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure. Reconfigurable scan networks are often hierarchical and may have complex structural and functional dependencies. Common approaches for scan verification based on static structural analysis and functional simulation are not sufficient to ensure correct operation of these types of architectures. To access an instrument in a reconfigurable scan network, a scan-in bit sequence must be generated according to the current state and structure of the network. Due to sequential and combinational dependencies, the access pattern generation process (pattern retargeting) poses a complex decision and optimization problem. This article presents the first generalized formal model that considers structural and functional dependencies of reconfigurable scan networks and is directly applicable to P1687-based and 1149.1-2013-based scan architectures. This model enables efficient formal verification of complex scan networks, as well as automatic generation of access patterns. The proposed pattern generation method supports concurrent access to multiple target scan registers (access merging) and generates short scan-in sequences.
BibTeX:
@article{BaranKW2015,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation}},
  journal = {ACM Transactions on Design Automation of Electronic Systems (TODAES)},
  year = {2015},
  volume = {20},
  number = {2},
  pages = {30:1--30:27},
  keywords = {Algorithms, Verification, Performance},
  abstract = {Efficient access to on-chip instrumentation is a key requirement for post-silicon validation, test, debug, bringup, and diagnosis. Reconfigurable scan networks, as proposed by e.g. IEEE P1687 and IEEE Std 1149.1-2013, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure. Reconfigurable scan networks are often hierarchical and may have complex structural and functional dependencies. Common approaches for scan verification based on static structural analysis and functional simulation are not sufficient to ensure correct operation of these types of architectures. To access an instrument in a reconfigurable scan network, a scan-in bit sequence must be generated according to the current state and structure of the network. Due to sequential and combinational dependencies, the access pattern generation process (pattern retargeting) poses a complex decision and optimization problem. This article presents the first generalized formal model that considers structural and functional dependencies of reconfigurable scan networks and is directly applicable to P1687-based and 1149.1-2013-based scan architectures. This model enables efficient formal verification of complex scan networks, as well as automatic generation of access patterns. The proposed pattern generation method supports concurrent access to multiple target scan registers (access merging) and generates short scan-in sequences.},
  doi = {http://dx.doi.org/10.1145/2699863},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/TODAES_BaranKW2015.pdf}
}
2. Access Port Protection for Reconfigurable Scan Networks
Baranowski, Rafal; Kochte, Michael A.; Wunderlich, Hans-Joachim
Journal of Electronic Testing: Theory and Applications (JETTA)
Vol. 30(6), December 2014, pp. 711-723
2014 JETTA-TTTC Best Paper Award
2014
DOI URL PDF 
Keywords: Debug and diagnosis, reconfigurable scan network, IJTAG, IEEE P1687, secure DFT, hardware security
Abstract: Scan infrastructures based on IEEE Std. 1149.1 (JTAG), 1500 (SECT), and P1687 (IJTAG) provide a cost-effective access mechanism for test, reconfiguration, and debugging purposes. The improved accessibility of on-chip instruments, however, poses a serious threat to system safety and security. While state-of-theart protection methods for scan architectures compliant with JTAG and SECT are very effective, most of these techniques face scalability issues in reconfigurable scan networks allowed by the upcoming IJTAG standard. This paper describes a scalable solution for multilevel access management in reconfigurable scan networks. The access to protected instruments is restricted locally at the interface to the network. The access restriction is realized by a sequence filter that allows only a precomputed set of scan-in access sequences. This approach does not require any modification of the scan architecture and causes no access time penalty. Therefore, it is well suited for core-based designs with hard macros and 3D integrated circuits. Experimental results for complex reconfigurable scan networks show that the area overhead depends primarily on the number of allowed accesses, and is marginal even if this number exceeds the count of registers in the network.
BibTeX:
@article{BaranKW2014a,
  author = {Baranowski, Rafal and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Access Port Protection for Reconfigurable Scan Networks}},
  journal = {Journal of Electronic Testing: Theory and Applications (JETTA)},
  publisher = {Springer-Verlag},
  year = {2014},
  volume = {30},
  number = {6},
  pages = {711--723},
  keywords = {Debug and diagnosis, reconfigurable scan network, IJTAG, IEEE P1687, secure DFT, hardware security},
  abstract = {Scan infrastructures based on IEEE Std. 1149.1 (JTAG), 1500 (SECT), and P1687 (IJTAG) provide a cost-effective access mechanism for test, reconfiguration, and debugging purposes. The improved accessibility of on-chip instruments, however, poses a serious threat to system safety and security. While state-of-theart protection methods for scan architectures compliant with JTAG and SECT are very effective, most of these techniques face scalability issues in reconfigurable scan networks allowed by the upcoming IJTAG standard. This paper describes a scalable solution for multilevel access management in reconfigurable scan networks. The access to protected instruments is restricted locally at the interface to the network. The access restriction is realized by a sequence filter that allows only a precomputed set of scan-in access sequences. This approach does not require any modification of the scan architecture and causes no access time penalty. Therefore, it is well suited for core-based designs with hard macros and 3D integrated circuits. Experimental results for complex reconfigurable scan networks show that the area overhead depends primarily on the number of allowed accesses, and is marginal even if this number exceeds the count of registers in the network.},
  url = { http://link.springer.com/article/10.1007/s10836-014-5484-2 },
  doi = {http://dx.doi.org/10.1007/s10836-014-5484-2},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/JETTA_BaranKW2014.pdf}
}
1. High Quality System Level Test and Diagnosis
Jutman, Artur; Sonza Reorda, Matteo; Wunderlich, Hans-Joachim
Proceedings of the 23rd IEEE Asian Test Symposium (ATS'14), Hangzhou, China, 16-19 November 2014, pp. 298-305
2014
DOI PDF 
Keywords: System test, board test, diagnosis
Abstract: This survey introduces into the common practices, current challenges and advanced techniques of high quality system level test and diagnosis. Specialized techniques and industrial standards of testing complex boards are introduced. The reuse for system test of design for test structures and test data developed at chip level is discussed, including the limitations and research challenges. Structural test methods have to be complemented by functional test methods. State-of-the-art and leading edge research for functional testing will be covered.
BibTeX:
@inproceedings{JutmaSW2014,
  author = {Jutman, Artur and Sonza Reorda, Matteo and Wunderlich, Hans-Joachim},
  title = {{High Quality System Level Test and Diagnosis}},
  booktitle = {Proceedings of the 23rd IEEE Asian Test Symposium (ATS'14)},
  year = {2014},
  pages = {298--305},
  keywords = {System test, board test, diagnosis},
  abstract = {This survey introduces into the common practices, current challenges and advanced techniques of high quality system level test and diagnosis. Specialized techniques and industrial standards of testing complex boards are introduced. The reuse for system test of design for test structures and test data developed at chip level is discussed, including the limitations and research challenges. Structural test methods have to be complemented by functional test methods. State-of-the-art and leading edge research for functional testing will be covered.},
  doi = {http://dx.doi.org/10.1109/ATS.2014.62},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ATS_JutmaSW2014.pdf}
}
Created by JabRef on 14/04/2022.
Workshop Contributions
Matching entries: 0
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1. Autonomous Testing for 3D-ICs with IEEE Std. 1687
Ye, Jin-Cun; Kochte, Michael A.; Lee, Kuen-Jong; Wunderlich, Hans-Joachim
First International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium, Amsterdam, The Netherlands, 26-27 May 2016
2016
 
BibTeX:
@inproceedings{YeKLW2016,
  author = {Ye, Jin-Cun and Kochte, Michael A. and Lee, Kuen-Jong and Wunderlich, Hans-Joachim},
  title = {{Autonomous Testing for 3D-ICs with IEEE Std. 1687}},
  booktitle = {First International Test Standards Application Workshop (TESTA), co-located with IEEE European Test Symposium},
  year = {2016}
}
Created by JabRef on 14/04/2022.

 

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