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FAST – Zuverlässigkeitsbewertung durch „Faster-than-at-Speed Test“

seit 02.2017, DFG-Projekt: WU 245/19-1   

Moderne Fertigungstechnologien in der Nanoelektronik integrieren Milliarden von Transistoren mit Abmessungen von 14 Nanometern und darunter in einem Chip. Dies ermöglicht grundlegend neue Herangehensweisen und Lösungen in vielen Bereichen, bringt aber gleichzeitig fundamentale Herausforderungen mit sich. Ein zentrales Problem sind Frühausfälle, die immer wieder Rückrufaktionen erfordern und dadurch Kosten in Milliardenhöhe verursachen. Ein wichtiger Grund hierfür sind sogenannte schwache Schaltungsstrukturen, die zwar bei der Inbetriebnahme funktionieren, aber der späteren Belastung im Betrieb nicht gewachsen sind. Während sich andere Ausfallursachen, wie etwa Alterung oder externe Störungen durch einen robusten Entwurf bis zu einem gewissen Umfang kompensieren lassen, müssen drohende Frühausfälle durch Tests erkannt und betroffene Systeme aussortiert werden. Dazu werden Verfahren benötigt, die weit über den heutigen Stand der Technik hinausgehen.

Da die schwachen Schaltungsstrukturen unter Betriebsbedingungen zunächst korrekt funktionieren, müssen sie anhand nichtfunktionaler Indikatoren identifiziert werden. Neben dem Stromverbrauch im Ruhezustand und bei Schaltvorgängen sowie dem Verhalten bei variierender Betriebsspannung gehört das Zeitverhalten zu den wichtigsten Zuverlässigkeitsindikatoren. Im Hochgeschwindigkeitsbetrieb können kleine Abweichungen im Zeitverhalten einzelner Transistoren gemessen und als Fehlerindikator verwendet werden. Da hierfür ein Mehrfaches der eigentlichen Betriebsfrequenz angelegt werden muss, lassen sich herkömmliche Testmethoden nur sehr eingeschränkt einsetzen. Stattdessen müssen in folgenden drei Bereichen neue Methoden entwickelt und untersucht werden:

  1. Die Schaltung muss mit besonderen Ausstattungen für den prüfgerechten Entwurf (Design for Test / DFT) und den Selbsttest versehen werden, die auch bei Frequenzen jenseits der funktionalen Spezifikation arbeiten können.
  2. Der Testablauf muss so geplant werden, dass bei einer möglichst geringen Zahl von Testfrequenzen eine maximale Fehlererfassung in kurzer Zeit möglich wird.
  3. Mit einer geeigneten Metrik müssen quantitative Aussagen über die Erfassung möglicher schwacher Schaltungsteile getroffen werden. Eine besondere Schwierigkeit liegt hier in der Unterscheidung zwischen tatsächlich fehleranfälligen Strukturen und Abweichungen aufgrund zunehmender Variationen in der Nanoskalierung.

Da ein Hochgeschwindigkeitstest ganz besondere Anforderungen an externe Testautomaten stellt, ist es wesentlich, ihn durch eingebauten Selbsttest (Built-in Self-Test / BIST) zu unterstützen und auszuführen.

Mit der Lösung der drei genannten Probleme wird den immens steigenden nicht mehr wirtschaftlichen Kosten bei der Inbetriebnahme nanoskalierter Systeme, etwa durch „Burn-in“-Tests, begegnet und deren Einsatz in neuen Anwendungsbereichen unterstützt.

 

Publikationen

Journale und Tagungsberichte
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14. Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection
Najafi-Haghi, Zahra Paria; Klemme, Florian; Jafarzadeh, Hanieh; Amrouch, Hussam; Wunderlich, Hans-Joachim
To appear in Proceedings of the IEEE Conference on Design, Automation & Test in Europe (DATE'23), Antwerp, Belgium, Apr. 2023
2023
 
BibTeX:
@inproceedings{Najafi2023DATE,
  author = {Najafi-Haghi, Zahra Paria and Klemme, Florian and Jafarzadeh, Hanieh and Amrouch, Hussam and Wunderlich, Hans-Joachim},
  title = {{Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection}},
  booktitle = {To appear in Proceedings of the IEEE Conference on Design, Automation & Test in Europe (DATE'23)},
  year = {2023}
}
13. Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning
Liao, Yiwen; Najafi-Haghi, Zahra Paria; Wunderlich, Hans-Joachim; Yang, Bin
Proceedings of the IEEE International Test Conference (ITC'22), Anaheim, CA, USA, 25-30 September 2022
2022
 
Keywords: resistive open defect identification, deep learning, unsupervised learning
Abstract: Both process variations and defects in cells can lead to additional small delays within specifications, while the latter must be identified because they may degrade soon into critical faults for circuits and result in threat to reliability. Therefore, discriminating small delays due to defects from those due to variations has drawn increasingly attention in the test community over the recent years. One promising research direction is to formulate the task into binary classification by using delays under a few supply voltages as the only variables for datadriven algorithms. However, many approaches often assume the availability of delay information from both defective and nondefective cells or combinational circuits. This assumption implies a large time consumption for simulation, and considerable costs for manufactured defective devices. To address the issues above, this paper proposes to use unsupervised deep learning technique to train an recognizer on non-defective data only but still can identify defects during inference. Specifically, we have proposed weighted autoencoder with a novel data augmentation technique to solve this problem. Experiments show that our approach has comparable detection capability as supervised learning schemes, while our method does not require any defective data. Moreover, our approach is more robust to unbalanced datasets and to nontarget defects than other methods.
BibTeX:
@inproceedings{LiaoNW22,
  author = {Liao, Yiwen and Najafi-Haghi, Zahra Paria and Wunderlich, Hans-Joachim and Yang, Bin},
  title = {{Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'22)},
  year = {2022},
  keywords = {resistive open defect identification, deep learning, unsupervised learning},
  abstract = {Both process variations and defects in cells can lead to additional small delays within specifications, while the latter must be identified because they may degrade soon into critical faults for circuits and result in threat to reliability. Therefore, discriminating small delays due to defects from those due to variations has drawn increasingly attention in the test community over the recent years. One promising research direction is to formulate the task into binary classification by using delays under a few supply voltages as the only variables for datadriven algorithms. However, many approaches often assume the availability of delay information from both defective and nondefective cells or combinational circuits. This assumption implies a large time consumption for simulation, and considerable costs for manufactured defective devices. To address the issues above, this paper proposes to use unsupervised deep learning technique to train an recognizer on non-defective data only but still can identify defects during inference. Specifically, we have proposed weighted autoencoder with a novel data augmentation technique to solve this problem. Experiments show that our approach has comparable detection capability as supervised learning schemes, while our method does not require any defective data. Moreover, our approach is more robust to unbalanced datasets and to nontarget defects than other methods.}
}
12. On Extracting Reliability Information from Speed Binning
Najafi-Haghi, Zahra Paria; Klemme, Florian; Amrouch, Hussam; Wunderlich, Hans-Joachim
Proceedings of the 27th IEEE European Test Symposium (ETS’22), Barcelona, Spain, 23-27 May 2022
2022
DOI PDF 
Keywords: Resistive open defects, small delay faults, reliability, speed binning, static timing analysis, machine learning
Abstract: Adaptive Voltage Frequency Scaling (AVFS) is an important means to overcome process-induced variability challenges for advanced high-performance circuits. AVFS requires and allows determining the maximum speed Fmax(Vdd) reachable under a set of certain operation voltages Vdd. In this paper, it is shown that the Fmax(Vdd) measurements contain relevant data to identify some hidden defects in a chip which are reliability threats and can cause device failures, but pass the speed binning procedure within the given specifications.
Static Timing Analysis (STA) is applied to a circuit designed by using standard cell libraries in which the underlying transistors along with process variations have been carefully calibrated against industrial 14nm FinFET measurement data, and instances with and without injected small resistive open defects are generated. From the slope of the function Fmax(Vdd), a machine learning procedure can identify some defects with high accuracy and few false positives. These chips can be then discarded without any further need and cost for testing. It has to be noted that this reliability information comes for free from the data which is already generated, and does not need any additional measurements.
BibTeX:
@inproceedings{NajafKAW22,
  author = {Najafi-Haghi, Zahra Paria and Klemme, Florian and Amrouch, Hussam and Wunderlich, Hans-Joachim},
  title = {{On Extracting Reliability Information from Speed Binning}},
  booktitle = {Proceedings of the 27th IEEE European Test Symposium (ETS’22)},
  year = {2022},
  keywords = {Resistive open defects, small delay faults, reliability, speed binning, static timing analysis, machine learning},
  abstract = {Adaptive Voltage Frequency Scaling (AVFS) is an important means to overcome process-induced variability challenges for advanced high-performance circuits. AVFS requires and allows determining the maximum speed Fmax(Vdd) reachable under a set of certain operation voltages Vdd. In this paper, it is shown that the Fmax(Vdd) measurements contain relevant data to identify some hidden defects in a chip which are reliability threats and can cause device failures, but pass the speed binning procedure within the given specifications.
Static Timing Analysis (STA) is applied to a circuit designed by using standard cell libraries in which the underlying transistors along with process variations have been carefully calibrated against industrial 14nm FinFET measurement data, and instances with and without injected small resistive open defects are generated. From the slope of the function Fmax(Vdd), a machine learning procedure can identify some defects with high accuracy and few false positives. These chips can be then discarded without any further need and cost for testing. It has to be noted that this reliability information comes for free from the data which is already generated, and does not need any additional measurements.}, doi = {http://dx.doi.org/10.1109/ETS54262.2022.9810443}, file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2022/ETS_NajafKAW2022.pdf} }
11. Stress-Aware Periodic Test of Interconnects
Somayeh, Sadeghi-Kohan; Hellebrand, Sybille; Wunderlich, Hans-Joachim
Journal of Electronic Testing: Theory and Applications (JETTA), January 2022
2022
DOI PDF 
Keywords: Periodic Test, Functional Safety, Hidden Inter-connect Defect, Electro-Migration, Multi-frequency Test
Abstract: Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for ran- dom logic. The paper at hand extends this approach to inter- connect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.
BibTeX:
@article{SomayHW22,
  author = {Somayeh, Sadeghi-Kohan and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Stress-Aware Periodic Test of Interconnects}},
  journal = {Journal of Electronic Testing: Theory and Applications (JETTA)},
  year = {2022},
  keywords = {Periodic Test, Functional Safety, Hidden Inter-connect Defect, Electro-Migration, Multi-frequency Test},
  abstract = {Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for ran- dom logic. The paper at hand extends this approach to inter- connect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.},
  doi = {http://dx.doi.org/10.1007/s10836-021-05979-5},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2022/JETTA_SomayHW2022.pdf}
}
10. Resistive Open Defect Classification of Embedded Cells under Variations
Najafi-Haghi, Zahra Paria; Wunderlich, Hans-Joachim
Proceedings of the IEEE Latin-American Test Symposium (LATS'21), Virtual, 27 - 29 October 2021, pp. 1-6
2021
DOI PDF 
Abstract: Small Delay Faults (SDFs) due to defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is in the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its behavioral features are affected by several masking impacts of the rest of the circuit. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defect devices without a major impact on yield.
BibTeX:
@inproceedings{NajafW2021,
  author = {Najafi-Haghi, Zahra Paria and Wunderlich, Hans-Joachim},
  title = {{Resistive Open Defect Classification of Embedded Cells under Variations}},
  booktitle = {Proceedings of the IEEE Latin-American Test Symposium (LATS'21)},
  year = {2021},
  pages = {1--6},
  abstract = {Small Delay Faults (SDFs) due to defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is in the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its behavioral features are affected by several masking impacts of the rest of the circuit. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defect devices without a major impact on yield.},
  doi = {http://dx.doi.org/10.1109/LATS53581.2021.9651857},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2021/LATS_NajafW2021.pdf}
}
9. Logic Fault Diagnosis of Hidden Delay Defects
Holst, Stefan; Kampmann, Matthias; Sprenger, Alexander; Reimer, Jan Dennis; Hellebrand, Sybille; Wunderlich, Hans-Joachim; Wen, Xiaoqing
Proceedings of the IEEE International Test Conference (ITC'20), 1-6 November 2020
2020
DOI PDF 
Abstract: Hidden delay defects (HDDs) are small delay defects that pass all at-speed tests at nominal capture time. They are an important indicator of latent defects that lead to early-life failures and aging problems that are serious especially in autonomous and medical applications. An effective way to screen out HDDs is to use Faster-than-At-Speed Testing (FAST) to observe outputs of sensitized non-critical paths which are expected to be stable earlier than nominal capture time.To improve the reliability of current and future designs, it is important to learn about the population of HDDs using logic diagnosis. We present the very first logic fault diagnosis technique that is able to identify HDDs by analyzing fail logs produced by FAST.Even with aggressive FAST testing, HDDs generate only very few failing test response bits. To overcome this severe challenge, we propose new backtracing and response matching methods that yield high diagnostic success rates even with very limited amount of failure data. The performance and scalability of our HDD diagnosis method is validated using fault injection campaigns with large benchmark circuits.
BibTeX:
@inproceedings{HolstKSRHWW2020,
  author = {Holst, Stefan and Kampmann, Matthias and Sprenger, Alexander and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim and Wen, Xiaoqing},
  title = {{Logic Fault Diagnosis of Hidden Delay Defects}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'20)},
  year = {2020},
  abstract = {Hidden delay defects (HDDs) are small delay defects that pass all at-speed tests at nominal capture time. They are an important indicator of latent defects that lead to early-life failures and aging problems that are serious especially in autonomous and medical applications. An effective way to screen out HDDs is to use Faster-than-At-Speed Testing (FAST) to observe outputs of sensitized non-critical paths which are expected to be stable earlier than nominal capture time.To improve the reliability of current and future designs, it is important to learn about the population of HDDs using logic diagnosis. We present the very first logic fault diagnosis technique that is able to identify HDDs by analyzing fail logs produced by FAST.Even with aggressive FAST testing, HDDs generate only very few failing test response bits. To overcome this severe challenge, we propose new backtracing and response matching methods that yield high diagnostic success rates even with very limited amount of failure data. The performance and scalability of our HDD diagnosis method is validated using fault injection campaigns with large benchmark circuits.},
  doi = {http://dx.doi.org/10.1109/ITC44778.2020.9325234},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2020/ITC_HolstKSRHWW2020.pdf}
}
8. Variation-Aware Defect Characterization at Cell Level
Najafi-Haghi, Zahra Paria; Hashemipour-Nazari, Marzieh; Wunderlich, Hans-Joachim
Proceedings of the 25th IEEE European Test Symposium (ETS'20), Tallinn, Estonia, 25-29 May 2020, pp. 1-6
2020
DOI PDF 
Abstract: Small Delay Faults (SDFs) are an indicator of reliability threats even if they do not affect the behavior of a system at nominal speed. Various defects may evolve over time into a complete system failure, and defects have to be distinguished from delays due to process variations which also change the circuit timing but are benign. Based on Monte-Carlo electrical simulation at cell level, in this work it is shown that a few measurements at different operating points of voltage and frequency are sufficient to identify a defect cell even if its behavior is completely within the specification range. The developed classifier is based on statistical learning and can be annotated to each element of a cell library to support manufacturing test, diagnosis and optimizing the burn-in process or yield.
BibTeX:
@inproceedings{NajafiHW2020,
  author = {Najafi-Haghi, Zahra Paria and Hashemipour-Nazari, Marzieh and Wunderlich, Hans-Joachim},
  title = {{Variation-Aware Defect Characterization at Cell Level}},
  booktitle = {Proceedings of the 25th IEEE European Test Symposium (ETS'20)},
  year = {2020},
  pages = {1--6},
  abstract = {Small Delay Faults (SDFs) are an indicator of reliability threats even if they do not affect the behavior of a system at nominal speed. Various defects may evolve over time into a complete system failure, and defects have to be distinguished from delays due to process variations which also change the circuit timing but are benign. Based on Monte-Carlo electrical simulation at cell level, in this work it is shown that a few measurements at different operating points of voltage and frequency are sufficient to identify a defect cell even if its behavior is completely within the specification range. The developed classifier is based on statistical learning and can be annotated to each element of a cell library to support manufacturing test, diagnosis and optimizing the burn-in process or yield.},
  doi = {http://dx.doi.org/10.1109/ETS48528.2020.9131600},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2020/ETS_NajafHW2020.pdf}
}
7. Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling
Schneider, Eric; Wunderlich, Hans-Joachim
Proceedings of the IEEE VLSI Test Symposium (VTS'20), San Diego, US, 5-8 April 2020, pp. 1-6
2020
DOI PDF 
Abstract: Systems with adaptive voltage-and frequency scaling (AVFS) require timing validation with accurate timing models under multiple operating points. Since, these models are typically simulated at logic level and extremely time-consuming, the state-of-the-art often compromises both accuracy and speed. This paper presents the first massively parallel switch level time simulator with parametric delay modeling for efficient timing-accurate validation of systems with AVFS. It provides full glitch-accurate switching activity information of designs under varying supply voltage and temperature. Offline statistical learning with regression analysis is employed to generate polynomials for dynamic delay modeling by approximation of the first-order electrical parameters of CMOS standard cells. With the parallelization on graphics processing units and simultaneous exploitation of multiple dimensions of parallelism the simulation throughput is maximized and scalable-design space exploration of AVFS-based systems is enabled. Results demonstrate the efficiency and accuracy with speedups of up to 159x over conventional logic level time simulation with static delays.
BibTeX:
@inproceedings{SchneW2020a,
  author = {Schneider, Eric and Wunderlich, Hans-Joachim},
  title = {{Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling}},
  booktitle = {Proceedings of the IEEE VLSI Test Symposium (VTS'20)},
  year = {2020},
  pages = {1--6},
  abstract = {Systems with adaptive voltage-and frequency scaling (AVFS) require timing validation with accurate timing models under multiple operating points. Since, these models are typically simulated at logic level and extremely time-consuming, the state-of-the-art often compromises both accuracy and speed. This paper presents the first massively parallel switch level time simulator with parametric delay modeling for efficient timing-accurate validation of systems with AVFS. It provides full glitch-accurate switching activity information of designs under varying supply voltage and temperature. Offline statistical learning with regression analysis is employed to generate polynomials for dynamic delay modeling by approximation of the first-order electrical parameters of CMOS standard cells. With the parallelization on graphics processing units and simultaneous exploitation of multiple dimensions of parallelism the simulation throughput is maximized and scalable-design space exploration of AVFS-based systems is enabled. Results demonstrate the efficiency and accuracy with speedups of up to 159x over conventional logic level time simulation with static delays.},
  doi = {http://dx.doi.org/10.1109/VTS48691.2020.9107642},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2020/VTS_SchneW2020.pdf}
}
6. Using Programmable Delay Monitors for Wear-Out and Early Life Failure Prediction
Liu, Chang; Schneider, Eric; Wunderlich, Hans-Joachim.
Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'20), Grenoble, FR, 9-13 March 2020, pp. 1-6
2020
DOI PDF 
Abstract: Early life failures in marginal devices are a severe reliability threat in current nano-scaled CMOS devices. While small delay faults are an effective indicator of marginalities, their detection requires special efforts in testing by so-called Faster-than-At-Speed Test (FAST). In a similar way, delay degradation is an indicator that a device reaches the wear-out phase due to aging. Programmable delay monitors provide the possibility to detect gradual performance changes in a system and allow to observe device degradation.This paper presents a unified approach to test small delay faults related to wear-out and early-life failures by reuse of existing programmable delay monitors within FAST. The approach is complemented by a test-scheduling which optimally selects frequencies and delay configurations to significantly increase the fault coverage of small delays and to reduce the test time.
BibTeX:
@inproceedings{LiuSW2020,
  author = {Liu, Chang and Schneider, Eric and Wunderlich, Hans-Joachim.},
  title = {{Using Programmable Delay Monitors for Wear-Out and Early Life Failure Prediction}},
  booktitle = {Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'20)},
  year = {2020},
  pages = {1--6},
  abstract = {Early life failures in marginal devices are a severe reliability threat in current nano-scaled CMOS devices. While small delay faults are an effective indicator of marginalities, their detection requires special efforts in testing by so-called Faster-than-At-Speed Test (FAST). In a similar way, delay degradation is an indicator that a device reaches the wear-out phase due to aging. Programmable delay monitors provide the possibility to detect gradual performance changes in a system and allow to observe device degradation.This paper presents a unified approach to test small delay faults related to wear-out and early-life failures by reuse of existing programmable delay monitors within FAST. The approach is complemented by a test-scheduling which optimally selects frequencies and delay configurations to significantly increase the fault coverage of small delays and to reduce the test time.},
  doi = {http://dx.doi.org/10.23919/DATE48585.2020.9116284},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2020/DATE_LiuSW2020.pdf}
}
5. GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling
Schneider, Eric; Wunderlich, Hans-Joachim
Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'20), Grenoble, FR, 9-13 March 2020, pp. 1-6
2020
DOI PDF 
Abstract: Timing validation of systems with adaptive voltage-and frequency scaling (AVFS) requires an accurate timing model under multiple operating points. Simulating such a model at gate level is extremely time-consuming, and the state-of-the-art compromises both accuracy and compute efficiency.This paper presents a method for dynamic gate delay modeling on graphics processing unit (GPU) accelerators which is based on polynomial approximation with offline statistical learning using regression analysis. It provides glitch-accurate switching activity information for gates and designs under varying supply voltages with negligible memory and performance impact. Parallelism from the evaluation of operating conditions, gates and stimuli is exploited simultaneously to utilize the high arithmetic computing throughput of GPUs. This way, large-scale design space exploration of AVFS-based systems is enabled. Experimental results demonstrate the efficiency and accuracy of the presented approach showing speedups of three orders of magnitude over conventional time simulation that supports static delays only.
BibTeX:
@inproceedings{SchneW2020,
  author = {Schneider, Eric and Wunderlich, Hans-Joachim},
  title = {{GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling}},
  booktitle = {Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'20)},
  year = {2020},
  pages = {1--6},
  abstract = {Timing validation of systems with adaptive voltage-and frequency scaling (AVFS) requires an accurate timing model under multiple operating points. Simulating such a model at gate level is extremely time-consuming, and the state-of-the-art compromises both accuracy and compute efficiency.This paper presents a method for dynamic gate delay modeling on graphics processing unit (GPU) accelerators which is based on polynomial approximation with offline statistical learning using regression analysis. It provides glitch-accurate switching activity information for gates and designs under varying supply voltages with negligible memory and performance impact. Parallelism from the evaluation of operating conditions, gates and stimuli is exploited simultaneously to utilize the high arithmetic computing throughput of GPUs. This way, large-scale design space exploration of AVFS-based systems is enabled. Experimental results demonstrate the efficiency and accuracy of the presented approach showing speedups of three orders of magnitude over conventional time simulation that supports static delays only.},
  doi = {http://dx.doi.org/10.23919/DATE48585.2020.9116256},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2020/DATE_SchneW2020.pdf}
}
4. Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses
Holst, Stefan; Schneider, Eric; Kochte, Michael A.; Wen, Xiaoqing; Wunderlich, Hans Joachim
Proceedings of the IEEE International Test Conference (ITC'19), Washington DC, USA, 11-15 November 2019
2019
DOI PDF 
Keywords: small delay defect, logic diagnosis, test response compaction, process variation, GP-GPU
Abstract: With today’s tight timing margins, increasing manufacturing variations, and new defect behaviors in FinFETs, effective yield learning requires detailed information on the population of small delay defects in fabricated chips. Small delay fault diagnosis for yield learning faces two principal challenges: (1) production test responses are usually highly compacted reducing the amount of available failure data, and (2) failure signatures not only depend on the actual defect but also on omnipresent and unknown delay variations. This work presents the very first diagnosis algorithm specifically designed to diagnose timing issues on compacted failure data and under process variations. An innovative combination of variation-invariant structural anal- ysis, GPU-accelerated time-simulation, and variation-tolerant syndrome matching for compacted test responses allows the proposed algorithm to cope with both challenges. Experiments on large benchmark circuits clearly demonstrate the scalability and superior accuracy of the new diagnosis approach.
BibTeX:
@inproceedings{HolstSKWW2019,
  author = {Holst, Stefan and Schneider, Eric and Kochte, Michael A. and Wen, Xiaoqing and Wunderlich, Hans Joachim},
  title = {{Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'19)},
  year = {2019},
  keywords = {small delay defect, logic diagnosis, test response compaction, process variation, GP-GPU},
  abstract = {With today’s tight timing margins, increasing manufacturing variations, and new defect behaviors in FinFETs, effective yield learning requires detailed information on the population of small delay defects in fabricated chips. Small delay fault diagnosis for yield learning faces two principal challenges: (1) production test responses are usually highly compacted reducing the amount of available failure data, and (2) failure signatures not only depend on the actual defect but also on omnipresent and unknown delay variations. This work presents the very first diagnosis algorithm specifically designed to diagnose timing issues on compacted failure data and under process variations. An innovative combination of variation-invariant structural anal- ysis, GPU-accelerated time-simulation, and variation-tolerant syndrome matching for compacted test responses allows the proposed algorithm to cope with both challenges. Experiments on large benchmark circuits clearly demonstrate the scalability and superior accuracy of the new diagnosis approach.},
  doi = {http://dx.doi.org/10.1109/ITC44170.2019.9000143},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2019/ITC_HolstSKWW2019.pdf}
}
3. Built-in Test for Hidden Delay Faults
Kampmann, Matthias; Kochte, Michael A.; Liu, Chang; Schneider, Eric; Hellebrand, Sybille; Wunderlich, Hans-Joachim
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Vol. 38(10), 2019, pp. 1956-1968
2019
DOI PDF 
Keywords: Faster-than-at-Speed-Test, BIST, in-field test, reliability
Abstract: Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster- than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test. This paper presents a fully autonomous built-in self-test (BIST) approach for FAST, which supports in-field testing by appropriate strategies for test generation and response compac- tion. In particular, the required test frequencies for hidden delay fault detection are selected, such that hardware overhead and test time are minimized. Furthermore, test response compaction handles the large number of unknowns (X-values) on long paths by storing intermediate MISR-signatures in a small on-chip memory for later analysis using X-canceling transformations. A comprehensive experimental study demonstrates the effectiveness of the presented approach. In particular, the impact of the considered fault size is studied in detail.
BibTeX:
@article{KampmKLSHW2018,
  author = {Kampmann, Matthias and Kochte, Michael A. and Liu, Chang and Schneider, Eric and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Built-in Test for Hidden Delay Faults}},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
  year = {2019},
  volume = {38},
  number = {10},
  pages = {1956--1968},
  keywords = {Faster-than-at-Speed-Test, BIST, in-field test, reliability},
  abstract = {Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster- than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test. This paper presents a fully autonomous built-in self-test (BIST) approach for FAST, which supports in-field testing by appropriate strategies for test generation and response compac- tion. In particular, the required test frequencies for hidden delay fault detection are selected, such that hardware overhead and test time are minimized. Furthermore, test response compaction handles the large number of unknowns (X-values) on long paths by storing intermediate MISR-signatures in a small on-chip memory for later analysis using X-canceling transformations. A comprehensive experimental study demonstrates the effectiveness of the presented approach. In particular, the impact of the considered fault size is studied in detail.},
  doi = {http://dx.doi.org/10.1109/TCAD.2018.2864255},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2019/TCAD_KampmKLSHW2019.pdf}
}
2. Extending Aging Monitors for Early Life and Wear-out Failure Prevention
Liu, Chang; Schneider, Eric; Kampmann, Matthias; Hellebrand, Sybille; Wunderlich, Hans-Joachim
Proceedings of the 27th IEEE Asian Test Symposium (ATS'18), Hefei, Anhui, China, 15-18 October 2018, pp. 92-97
2018
DOI PDF 
Keywords: Faster-than-at-speed test, small delay faults, aging monitors
Abstract: Aging monitors can indicate the wear-out phase of a semi-conductor device before it will actually fail, and allow the use of integrated circuits in applications with high safety and reliability demands. In the early phase of the lifecycle of integrated systems, small delay faults may indicate reliability problems and early life failures, even if they are smaller than the slack of any path and neither alter the functional behavior of a system nor violate any aging guardband. One option to detect this type of hidden delay faults (HDFs) is the application of a faster-than-at-speed-test (FAST). This paper shows that aging monitors can be extended at low cost to achieve high HDF test coverage with a reduction in test time during FAST. The result is a unified strategy to improve the reliability in both early and late phases of the system lifecycle.
BibTeX:
@inproceedings{LiuSKHW2018,
  author = {Liu, Chang and Schneider, Eric and Kampmann, Matthias and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Extending Aging Monitors for Early Life and Wear-out Failure Prevention}},
  booktitle = {Proceedings of the 27th IEEE Asian Test Symposium (ATS'18)},
  year = {2018},
  pages = {92--97},
  keywords = {Faster-than-at-speed test, small delay faults, aging monitors},
  abstract = {Aging monitors can indicate the wear-out phase of a semi-conductor device before it will actually fail, and allow the use of integrated circuits in applications with high safety and reliability demands. In the early phase of the lifecycle of integrated systems, small delay faults may indicate reliability problems and early life failures, even if they are smaller than the slack of any path and neither alter the functional behavior of a system nor violate any aging guardband. One option to detect this type of hidden delay faults (HDFs) is the application of a faster-than-at-speed-test (FAST). This paper shows that aging monitors can be extended at low cost to achieve high HDF test coverage with a reduction in test time during FAST. The result is a unified strategy to improve the reliability in both early and late phases of the system lifecycle.},
  doi = {http://dx.doi.org/10.1109/ATS.2018.00028},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2018/ATS_LiuSKHW2018.pdf}
}
1. Aging Monitor Reuse for Small Delay Fault Testing
Liu, Chang; Kochte, Michael A.; Wunderlich, Hans-Joachim
Proceedings of the 35th VLSI Test Symposium (VTS'17), Caesars Palace, Las Vegas, Nevada, USA, 9-12 April 2017, pp. 1-6
2017
DOI PDF 
Keywords: Delay monitoring, delay test, faster-than-at-speed test, stability checker, small delay fault, ATPG
Abstract: Small delay faults receive more and more attention, since they may indicate a circuit reliability marginality even if they do not violate the timing at the time of production. At-speed test and faster-than-at-speed test (FAST) are rather expensive tasks to test for such faults. The paper at hand avoids complex on-chip structures or expensive high-speed ATE for test response evaluation, if aging monitors which are integrated into the device under test anyway are reused. The main challenge in reusing aging monitors for FAST consists in possible false alerts at higher frequencies. While a certain test vector pair makes a delay fault observable at one monitor, it may also exceed the time slack in the fault free case at a different monitor which has to be masked. Therefore, a multidimensional optimizing problem has to be solved for minimizing the masking overhead and the number of test vectors while maximizing delay fault coverage.
BibTeX:
@inproceedings{LiuKW2017,
  author = {Liu, Chang and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Aging Monitor Reuse for Small Delay Fault Testing}},
  booktitle = {Proceedings of the 35th VLSI Test Symposium (VTS'17)},
  year = {2017},
  pages = {1--6},
  keywords = {Delay monitoring, delay test, faster-than-at-speed test, stability checker, small delay fault, ATPG},
  abstract = {Small delay faults receive more and more attention, since they may indicate a circuit reliability marginality even if they do not violate the timing at the time of production. At-speed test and faster-than-at-speed test (FAST) are rather expensive tasks to test for such faults. The paper at hand avoids complex on-chip structures or expensive high-speed ATE for test response evaluation, if aging monitors which are integrated into the device under test anyway are reused. The main challenge in reusing aging monitors for FAST consists in possible false alerts at higher frequencies. While a certain test vector pair makes a delay fault observable at one monitor, it may also exceed the time slack in the fault free case at a different monitor which has to be masked. Therefore, a multidimensional optimizing problem has to be solved for minimizing the masking overhead and the number of test vectors while maximizing delay fault coverage.},
  doi = {http://dx.doi.org/10.1109/VTS.2017.7928921},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2017/VTS_LiuKW2017.pdf}
}
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