@inproceedings{LiuSW2020,
  author = {Liu, Chang and Schneider, Eric and Wunderlich, Hans-Joachim.},
  title = {{Using Programmable Delay Monitors for Wear-Out and Early Life Failure Prediction}},
  booktitle = {Proceedings of the ACM/IEEE Conference on Design, Automation Test in Europe (DATE'20)},
  year = {2020},
  pages = {1--6},
  abstract = {Early life failures in marginal devices are a severe reliability threat in current nano-scaled CMOS devices. While small delay faults are an effective indicator of marginalities, their detection requires special efforts in testing by so-called Faster-than-At-Speed Test (FAST). In a similar way, delay degradation is an indicator that a device reaches the wear-out phase due to aging. Programmable delay monitors provide the possibility to detect gradual performance changes in a system and allow to observe device degradation.This paper presents a unified approach to test small delay faults related to wear-out and early-life failures by reuse of existing programmable delay monitors within FAST. The approach is complemented by a test-scheduling which optimally selects frequencies and delay configurations to significantly increase the fault coverage of small delays and to reduce the test time.},
  doi = {http://dx.doi.org/10.23919/DATE48585.2020.9116284},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2020/DATE_LiuSW2020.pdf}
}

@article{KampmKLSHW2018,
  author = {Kampmann, Matthias and Kochte, Michael A. and Liu, Chang and Schneider, Eric and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Built-in Test for Hidden Delay Faults}},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)},
  year = {2019},
  volume = {38},
  number = {10},
  pages = {1956--1968},
  keywords = {Faster-than-at-Speed-Test, BIST, in-field test, reliability},
  abstract = {Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster- than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test. This paper presents a fully autonomous built-in self-test (BIST) approach for FAST, which supports in-field testing by appropriate strategies for test generation and response compac- tion. In particular, the required test frequencies for hidden delay fault detection are selected, such that hardware overhead and test time are minimized. Furthermore, test response compaction handles the large number of unknowns (X-values) on long paths by storing intermediate MISR-signatures in a small on-chip memory for later analysis using X-canceling transformations. A comprehensive experimental study demonstrates the effectiveness of the presented approach. In particular, the impact of the considered fault size is studied in detail.},
  doi = {http://dx.doi.org/10.1109/TCAD.2018.2864255},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2019/TCAD_KampmKLSHW2019.pdf}
}

@inproceedings{LiuSKHW2018,
  author = {Liu, Chang and Schneider, Eric and Kampmann, Matthias and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
  title = {{Extending Aging Monitors for Early Life and Wear-out Failure Prevention}},
  booktitle = {Proceedings of the 27th IEEE Asian Test Symposium (ATS'18)},
  year = {2018},
  pages = {92--97},
  keywords = {Faster-than-at-speed test, small delay faults, aging monitors},
  abstract = {Aging monitors can indicate the wear-out phase of a semi-conductor device before it will actually fail, and allow the use of integrated circuits in applications with high safety and reliability demands. In the early phase of the lifecycle of integrated systems, small delay faults may indicate reliability problems and early life failures, even if they are smaller than the slack of any path and neither alter the functional behavior of a system nor violate any aging guardband. One option to detect this type of hidden delay faults (HDFs) is the application of a faster-than-at-speed-test (FAST). This paper shows that aging monitors can be extended at low cost to achieve high HDF test coverage with a reduction in test time during FAST. The result is a unified strategy to improve the reliability in both early and late phases of the system lifecycle.},
  doi = {http://dx.doi.org/10.1109/ATS.2018.00028},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2018/ATS_LiuSKHW2018.pdf}
}

@inproceedings{LiuKW2017,
  author = {Liu, Chang and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Aging Monitor Reuse for Small Delay Fault Testing}},
  booktitle = {Proceedings of the 35th VLSI Test Symposium (VTS'17)},
  year = {2017},
  pages = {1--6},
  keywords = {Delay monitoring, delay test, faster-than-at-speed test, stability checker, small delay fault, ATPG},
  abstract = {Small delay faults receive more and more attention, since they may indicate a circuit reliability marginality even if they do not violate the timing at the time of production. At-speed test and faster-than-at-speed test (FAST) are rather expensive tasks to test for such faults. The paper at hand avoids complex on-chip structures or expensive high-speed ATE for test response evaluation, if aging monitors which are integrated into the device under test anyway are reused. The main challenge in reusing aging monitors for FAST consists in possible false alerts at higher frequencies. While a certain test vector pair makes a delay fault observable at one monitor, it may also exceed the time slack in the fault free case at a different monitor which has to be masked. Therefore, a multidimensional optimizing problem has to be solved for minimizing the masking overhead and the number of test vectors while maximizing delay fault coverage.},
  doi = {http://dx.doi.org/10.1109/VTS.2017.7928921},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2017/VTS_LiuKW2017.pdf}
}

@inproceedings{LiuKW2015,
  author = {Liu, Chang and Kochte, Michael A. and Wunderlich, Hans-Joachim},
  title = {{Efficient Observation Point Selection for Aging Monitoring}},
  booktitle = {Proceedings of the 21st IEEE International On-Line Testing Symposium (IOLTS'15)},
  year = {2015},
  pages = {176--181},
  keywords = {Aging monitoring, delay monitoring, online test, concurrent test, stability checker, path selection},
  abstract = {Circuit aging causes a performance degradation and eventually a functional failure. It depends on the workload and the environmental condition of the system, which are hard to predict in early design phases resulting in pessimistic worst case design. Existing delay monitoring schemes measure the remaining slack of paths in the circuit, but cause a significant hardware penalty including global wiring. More importantly, the low sensitization ratio of long paths in applications may lead to a very low measurement frequency or even an unmonitored timing violation. In this work, we propose a delay monitor placement method by analyzing the topological circuit structure and sensitization of paths. The delay monitors are inserted at meticulously selected positions in the circuit, named observation points (OPs). This OP monitor placement method can reduce the number of inserted monitors by up to 98% compared to a placement at the end of long paths. The experimental validation shows the effectiveness of this aging indication, i.e. a monitor issues a timing alert always earlier than any imminent timing failure.},
  doi = {http://dx.doi.org/10.1109/IOLTS.2015.7229855},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/IOLTS_LiuKW2015.pdf}
}

@inproceedings{BaranFKLWT2015,
  author = { Baranowski, Rafal and Firouzi, Farshad and Kiamehr, Saman and Liu, Chang and Tahoori, Mehdi and Wunderlich, Hans-Joachim },
  title = {{On-Line Prediction of NBTI-induced Aging Rates}},
  booktitle = {Proceedings of the ACM/IEEE Conference on Design, Automation and Test in Europe (DATE'15)},
  year = {2015},
  pages = {589--592},
  keywords = {Representative critical gates, Workload monitoring, Aging prediction, NBTI},
  abstract = {Nanoscale technologies are increasingly susceptible to aging processes such as Negative-Bias Temperature Instability (NBTI) which undermine the reliability of VLSI systems. Existing monitoring techniques can detect the violation of safety margins and hence make the prediction of an imminent failure possible. However, since such techniques can only detect measurable degradation effects which appear after a relatively long period of system operation, they are not well suited to early aging prediction and proactive aging alleviation. This work presents a novel method for the monitoring of NBTI-induced degradation rate in digital circuits. It enables the timely adoption of proper mitigation techniques that reduce the impact of aging. The developed method employs machine learning techniques to find a small set of so called Representative Critical Gates (RCG), the workload of which is correlated with the degradation of the entire circuit. The workload of RCGs is observed in hardware using so called workload monitors. The output of the workload monitors is evaluated on-line to predict system degradation experienced within a configurable (short) period of time, e.g. a fraction of a second. Experimental results show that the developed monitors predict the degradation rate with an average error of only 1.6% at 4.2% area overhead.},
  url = { http://dl.acm.org/citation.cfm?id=2755886 },
  doi = {http://dx.doi.org/10.7873/DATE.2015.0940},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2015/DATE_BaranFKLTW2015.pdf}
}

@inproceedings{HelleIKKLW2014,
  author = {Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and Kochte, Michael A. and Liu, Chang and Wunderlich, Hans-Joachim},
  title = {{FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects}},
  booktitle = {Proceedings of the IEEE International Test Conference (ITC'14)},
  year = {2014},
  pages = {1--8},
  abstract = {Small delay faults may be an indicator of a reliability threat, even if they do not affect the system functionality yet. In recent years, Faster-than-at-Speed-Test (FAST) has become a feasible method to detect faults, which are hidden by the timing slack or by long critical paths in the combinational logic. FAST poses severe challenges to the automatic test equipment with respect to timing, performance, and resolution. In this paper, it is shown how logic built-in self-test (BIST) or embedded deterministic test can be used for an efficient FAST application. Running BIST just at a higher frequency is not an option, as outputs of long paths will receive undefined values due to set time violations and destroy the content of the signature registers. Instead, for a given test pattern sequence, faults are classified according to the optimal detection frequency. For each class, a MISR-based compaction scheme is adapted, such that the critical bits to be observed can be determined by algebraic computations. Experiments show that rather a small number of inter-mediate signatures have to be evaluated to observe a large fraction of hidden delay faults testable by the given test sequence.},
  doi = {http://dx.doi.org/10.1109/TEST.2014.7035360},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2014/ITC_HelleIKKLW2014.pdf}
}

@inproceedings{BaranCILW2013,
  author = {Baranowski, Rafal and Cook, Alejandro and Imhof, Michael E. and Liu, Chang and Wunderlich, Hans-Joachim},
  title = {{Synthesis of Workload Monitors for On-Line Stress Prediction}},
  booktitle = {Proceedings of the 16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'13)},
  year = {2013},
  pages = {137--142},
  keywords = {Reliability estimation, workload monitoring, aging prediction, NBTI},
  abstract = {Stringent reliability requirements call for monitoring mechanisms to account for circuit degradation throughout the complete system lifetime. In this work, we efficiently monitor the stress experienced by the system as a result of its current workload. To achieve this goal, we construct workload monitors that observe the most relevant subset of the circuit’s primary and pseudo-primary inputs and produce an accurate stress approximation. The proposed approach enables the timely adoption of
suitable countermeasures to reduce or prevent any deviation from the intended circuit behavior. The relation between monitoring accuracy and hardware cost can be adjusted according to design requirements. Experimental results show the efficiency of the proposed approach for the prediction of stress induced by Negative Bias Temperature Instability (NBTI) in critical and near-critical paths of a digital circuit.},
  url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6653596},
  doi = {http://dx.doi.org/10.1109/DFT.2013.6653596},
  file = {http://www.iti.uni-stuttgart.de/fileadmin/rami/files/publications/2013/DFTS_BaranCILW2013.pdf}
}

@inproceedings{HelleIKKLW2015,
  author = {Hellebrand, Sybille and Indlekofer, Thomas and Kampmann, Matthias and Kochte, Michael A. and Liu, Chang and Wunderlich, Hans-Joachim},
  title = {{Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler}},
  booktitle = {27th GI/GMM/ITG Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'15)},
  year = {2015}
}