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RA - Current Research Projects

FAST – Reliability Assessment using „Faster-than-at-Speed Test“

Project Page: FAST – Reliability Assessment using „Faster-than-at-Speed Test“

An important problem in modern technology nodes in nano-electronics are early life failures, which often cause recalls of shipped products and incur high costs.  An important root cause of such failures are marginal circuit structures, which pass a conventional manufacturing test, but are not able to cope with the later workload and stress in the field.  Such structures can be identified on the basis of non-functional indicators, in particular by testing the timing behavior.  For an effective and cost-efficient test of these indicators, the FAST project investigates novel scan designs and built-in self-test strategies for circuits, which can operate at frequencies beyond the functional specification to detect small deviations of the nominal timing behavior and thus potential early life failures.

since 2.2017, DFG-Project: WU 245/19-1   

SHIVA: Secure Hardware for Information Processing

Project page: SHIVA: Sichere Hardware in der Informationsverarbeitung

In the project „SHIVA: Secure Hardware for Information Processing“, coordinated by Prof. Dr. Wunderlich (Institut für Technische Informatik), novel design and verification methods are researched and developed to increase and assure the security of microelectronic hardware, used for instance in automobile, medical, or industrial applications. These methods will help to achieve increasing security requirements and prevent system manipulation, extraction of critical data or process information, and IP theft.

since 02.2016,    

ACCESS: Verification, Test, and Diagnosis of Advanced Scan Infrastructures

Project page: ACCESS: Verification, Test, and Diagnosis of Advanced Scan Infrastructures

VLSI designs incorporate specialized instrumentation for post-silicon validation and debug, volume test and diagnosis, as well as in-field system maintenance. Due to the increasing complexity, however, the embedded infrastructure and flexible access mechanisms such as Reconfigurable Scan Networks (RSNs) themselves become a dependability bottleneck.

While efficient verification, test, and diagnosis techniques exist for combinational and some classes of sequential circuits, Reconfigurable Scan Networks (RSNs) still pose a serious challenge. RSNs are controlled via a serial interface and exhibit deeply sequential behavior (cf. IJTAG, IEEE P1687). Due to complex combinational and sequential dependencies, RSNs are beyond the capabilities of existing algorithms for verification, test, and diagnosis which were developed for classical, non-reconfigurable scan networks. The goal of ACCESS is to establish a methodology for efficient verification, test and diagnosis of RSNs to meet stringent reliability, safety and security goals.

since 08.2014, DFG-Project: WU 245/17-1    

PARSIVAL: Parallel High-Throughput Simulations for Efficient Nanoelectronic Design and Test Validation

Project page: PARSIVAL: Parallel High-Throughput Simulations for Efficient Nanoelectronic Design and Test Validation

Design and test validation is one of the most important and complex tasks within modern semi-conductor product development cycles. The design validation process analyzes and assesses a developed design with respect to certain validation targets to ensure its compliance with given specifications and customer requirements. Test validation evaluates the defect coverage obtained by certain test strategies and assesses the quality of the products tested and delivered. The validation targets include both, functional and non-functional properties, as well as the complex interactions and interdependencies between them. The validation means rely mainly on compute-intensive simulations which require more and more highly parallel hardware acceleration.

In this project novel methods for versatile simulation-based VLSI design and test validation on high throughput data-parallel architectures will be developed, which enable a wide range of important state-of-the-art validation tasks for large circuits. In general, due to the nature of the design validation processes and due to the massive amount of data involved, parallelism and throughput-optimization are the keys for making design validation feasible for future industrial-sized designs. The main focus and key features lie in the structure of the simulation model, the abstraction level and the used algorithms, as well as their parallelization on data-parallel architectures. The simulation algorithms should be kept simple to run fast, yet accurate enough to produce acceptable and valuable data for cross-layer validation of complex digital systems.

since 10.2014, DFG-Project: WU 245/16-1    

RA - Completed Projects

HiPS: High-Performance Simulation for High Quality Small Delay Fault Testing

Project page: High-Performance Simulation (HiPS) for High Quality Small Delay Fault Testing

Project partner:  Department of Creative Informatics - Kyushu Institute of Technology

This project aims to find novel abstraction and algorithm mapping methods to allow highly accurate timing and NFP-aware simulation of multi-million gate circuits on data-parallel architectures such as graphics processing units (GPUs). The expected dramatic speedup compared to the existing state-of-the-art allows fault simulation of millions of faults and thousands of patterns. The increased accuracy of the simulation results allow to optimize test patterns w.r.t. test power and small delay defect coverage in presence of power noise, clock skew or even circuit variations.

01.2015 - 12.2016, DAAD/JSPS PPP Japan Project: #57155440  

OTERA: Online Test Strategies for Reliable Reconfigurable Architectures

Project page: Online Test Strategies for Reliable Reconfigurable Architectures

Dynamically reconfigurable architectures enable a major acceleration of diverse applications by changing and optimizing the structure of the system at runtime. Permanent and transient faults threaten the correct operation of such an architecture. This project aims to increase dependability of runtime reconfigurable systems by a novel system-level strategy for online tests and online adaptation to an impaired state. This will be achieved by (a) scheduling such that tests for reconfigurable resources are executed with minimal performance impact, (b) resource management such that partially faulty resources are used for components which do not require the faulty elements, and (c) online monitoring and error checking. To ensure reliable runtime reconfiguration, each reconfiguration process is thoroughly tested by a novel and efficient combination of online structural and functional tests. Compared to existing fault-tolerance approaches, our proposal avoids the large hardware overhead of structural redundancy schemes. The saved resources are available for further application acceleration. Still, the proposed scheme covers faults in the fabric, in the reconfigured application logic and errors in the process of reconfiguration. 

10.2010 - 06.2017, DFG-Project: WU 245/10-1, 10-2, 10-3   

Simulation on Reconfigurable Heterogeneous Computer Architectures

Project page: Simulation on Reconfigurable Heterogeneous Computer Architectures

Since the beginning of the DFG Cluster of Excellence "Simulation Technology" (SimTech) at the University of Stuttgart in 2008, the Institute of Computer Architecture and Computer Engineering (ITI, RA) is an active part of the research within the Stuttgart Research Center for Simulation Technology (SRC SimTech). The institute's research includes the development of fault tolerant simulation algorithms for new, tightly-coupled many-core computer architectures like GPUs, the acceleration of existing simulations on such architectures, as well as the mapping of complex simulation applications to innovative reconfigurable heterogeneous computer architectures

Within the research cluster, Hans-Joachim Wunderlich acts as a principal investigator (PI) and he co-coordinates the research activities of the SimTech Project Network PN2 "High-Performance Simulation across Computer Architectures". This project network is unique in terms of its interdisciplinary nature and its interfaces between the participating researchers and projects. Scientists from computer science, chemistry, physics and chemical engineering work together to develop and provide new solutions for some of the major challenges in simulation technology. The classes of computational problems treated within project network PN2 comprise quantum mechanics, molecular mechanics, electronic structure methods, molecular dynamics, Markov-chain Monte-Carlo simulations and polarizable force fields.

06.2008 - 10.2017, SimTech Cluster of Excellence   

RM-BIST: Reliability Monitoring and Managing Built-In Self Test

Project page: Reliability Monitoring and Managing Built-In Self Test

The main objective of the RM-BIST project is to extend Design for Test (DFT) circuitry, which is primarily used during manufacturing test of VLSI chips, to Design for Reliability (DFR) infrastructure. We take advantage of existing built-in self-test (BIST) circuitry and reuse it during lifetime operation to provide system monitoring and perform reliability prediction. Moreover, the modified BIST infrastructure is used to perform targeted reliability improvements. We identify, monitor, predict, and mitigate errors affecting the system reliability at different time scales to handle various reliability detractors (radiation-induced soft errors, intermittent faults due to process and runtime variations, transistor aging and electromigration). The goal is to provide runtime support for reliability screening and improvement by modifying and reusing existing DFT infrastructure with minimum costs.

07.2012 - 06.2015, DFG-Project: WU 245/13-1    

ROCK: Robust Network On Chip Communication Through Hierarchical Online Diagnosis and Reconfiguration

Project page: Robuste On-Chip-Kommunikation durch hierarchische Online-Diagnose und -Rekonfiguration

The project ROCK targets the analysis and the prototypical development of robust architectures and associated design practices for Networks-on-Chips. Thereby, it meets the challenges of increased susceptibility of on-chip communication infrastructures against the massive influences caused by escalating integration density. ROCK pursues the strategy of conducting fault detection, online diagnosis und specific reconfiguration to tackle faults in a hierarchical manner throughout all network layers, aiming at selecting an optimal combination of activities over all layers. The quality of potential solutions is measured by their energy-minimal compliance to assurances made with respect to the performability of the network. For this purpose, performability will be defined for the research area of NoCs, incorporating communication performance and fault statistics. Any algorithms and architectures for controlling and performing diagnosis and reconfiguration shall themselves be designed as fault tolerant. Furthermore, their operation shall be transparent to the application processes and minimize interference with regular NoC communication. A wide range of architectures will be investigated based on the enabling technology of NoC fault models and high-level NoC fault simulation.

 

08.2011 - 12.2015, DFG-Project: WU 245/12-1    

OASIS: Online Failure Prediction for Microelectronic Circuits Using Aging Signatures

Project page: Online Failure Prediction for Microelectronic Circuits Using Aging Signatures

Microelectronic circuits suffer from life-time limiting aging. In this project, online in-field methods to assess circuit performance and remaining life-time will be developed to predict failures due to aging processes.
Sensors and monitoring infrastructure are used to analyze both operating conditions as well as aging indicators so that a system failure can be early indicated and prevented by technical measures. Novel maintenance concepts based on failure prediction allow for a substantial simplification of established structural fault tolerance measures (e.g. redundancy concepts) even in safety-critical applications since specific counter measures can be applied before an actual aging induced failure.
With the aid of such an on-line monitoring the effective life-time of a microelectronic product can be significantly increased at low cost.

03.2011 - 12.2014, DFG-Project: WU 245/11-1    

INTESYS: Model-Based Test Generation for the Efficient Test of Hardware/Software Systems

Project page: Model-Based Test Generation for the Efficient Test of Hardware/Software Systems

Functionality in embedded systems is more and more realized by integrated hardware / software systems. Typically, these systems are strongly coupled with technical processes, as for instance the control of a vehicle, which show time-dependent, discrete-continuous dynamics. Testing for the correct functionality of their according design as well as of the final product contributes large sums to the production costs due to its complexity. An efficient method is required for the integrated test of hardware and software in these systems, which respects all the aspects of validation, debug, test and diadnosis.
Model-based development and test gains importance in research and also in industrial practice, as they support the systematic, stepwise refinement of requirements down to the implementation. By using models to describe the functionality of integrated hard- and software systems a higher efficiency of their test can be achieved. The central goal of this project is the generation of tests for the functionality and structure of an embedded hardware / software system from its system model along with an automatic evaluation and failure diagnosis.

10.2010 - 09.2013, DFG-Project: WU 245/9-1    

REALTEST: Test and Reliability of nanoelectronic Systems



Project page: Test and Reliability of nanoelectronic Systems

In nanoelectronic circuit technology, circuits exhibit a high susceptibility to soft errors not only in memory arrays, but also in memory elements in random logic. Consequently, a goal of this project is the development of an efficient soft error protection scheme that uses both time and space redundancy.

01.2006 - 07.2013, DFG-Project: WU 245/5-1, 5-2    

Diana: BMBF Project: End-to-End Diagnostic Capabilities for Automotive Electronics Systems

Project page: BMBF Project: End-to-End Diagnostic Capabilities for Automotive Electronics Systems

Together, AUDI AG, Continental AG, Infineon Technologies AG and ZMD AG are researching ways to improve the analytic and diagnostic capabilities of electronic control units (ECU) in motor vehicles. Through to 2013, the four partners, headed by Infineon, will work on ways to make error detection more precise and faults easier to rectify for automakers and repair shops. The project partners will be assisted by several research organizations and universities: the Fraunhofer Institute for Integrated Circuits in Dresden, the University of the Federal Armed Forces in Munich, and the Universities of Cottbus, Erlangen-Nuremberg, and Stuttgart.

07.2010 - 07.2013, BMBF-Project    

AUTOTEST: Structural Field Test for Automotive Applications

Innovations in the automotive industry are driven by the advances in electronics and the widespread use of electronic control units. The goal of this project is to make semiconductor test and diagnosis mechanisms available at the system level, so that system failures caused by semiconductor defects can be analyzed without delay.

Project Partner: Audi AG

06.2009 - 07.2013, AUDI-Project    

The DFX Project

Project page: DFX

DFX is a logic synthesis tool and gate level simulator for circuit descriptions in VHDL and other hardware description languages. Besides that, DFX contains modern fault simulators and automatic test pattern generators for computer aided testing of integrated circuits.

DAAD Project VIGONI: Combining Fault Tolerance and Offline Test Strategies for Nanoscaled Electronics

Project page: Combining Fault Tolerance and Offline Test Strategies for Nanoscaled Electronics

Project Partner: Dipartimento di Automatica e Informatica, Politecnico di Torino

01.2007 - 12.2009, DAAD/Vigoni-Project    

DIADEM: Eingebettete Diagnose- und Debugmethoden für VLSI Systeme in Nanometer-Technologie

Project page: Eingebettete Diagnose- und Debugmethoden für VLSI Systeme in Nanometer-Technologie

Modern manufacturing processes are subject to high variations and a high sensitivity during operation. This project addresses the need for innovative embedded diagnosis solutions for such systems to reduce time-to-market with reasonable costs.

06.2006 - 05.2009, DFG-Project: WU 245/4-1    

Researcher Group: Concepts and Methods for Reliability Evaluation of Mechatronic Systems in Early Development Phases

Project page: Concepts and Methods for Reliability Evaluation of Mechatronic Systems in Early Development Phases

Assuring a certain reliability level for mechatronic systems becomes more and more important as human life is affected by it. For a careful estimation of the system reliability not only the reliability of each individual component has to be taken into account but also the interaction among the components. In this project, tools and methodologies to improve reliability on the electronic layer of such systems are developed.

09.2002 - 12.2009, DFG-Researcher Group: WU 245/3-1, 3-2, 3-3    

IBM CAS Project: Improved Testing of VLSI Chips with Power Constraints



Project page: Improved Testing of VLSI Chips with Power Constraints

The elevated power dissipation during test has severe impact on test time, test reliability and product reliability, especially for high-performance processors like the Cell Processor.
In the course of this project, new methods for test planning that take advantage of clock gating and power gating are developed.

Project Partner: IBM Deutschland Entwicklung, IBM CAS

10.2005 - 12.2009, IBM CAS-Project    

MAYA: Neue Methoden für den Massiv-Parallel-Test im Hochvolumen, Yield Learning und beste Testqualität



Project page: Neue Methoden für den Massiv-Parallel-Test im Hochvolumen, Yield Learning und beste Testqualität

High-end digital circuits need a very large amount of test vectors. Given such high data volumes, test cost is predicted to explode by a factor of 120.
This project addresses this challenge by developing and integrating innovative technology for generating and capturing data on-chip.

Project Partner: NXP Semiconductors, Hamburg

05.2006 - 04.2009, BMBF-Project    

VIVA / LEISTE: Power Conscious Online Test

Project page: Power Conscious Online Test

This project tackles issues regarding power consumption during self-test of microprocessors. A new method is proposed which achieves high fault coverage, short test time with a small power/energy budget on the target system.

03.2003 - 10.2005, DFG-Project: WU 245/2-2    

AZTEKE: Extended Deterministic Logic Built-In Self-Test

Project page: Extended Deterministic Logic Built-In Self-Test

Project Partner: Philips Semiconductors, Hamburg - Germany

03.2002 - 02.2005, BMBF-Project: 01M3063C    

DLBIST Method: Deterministic Built-In Self-Test

Project page: Deterministic Built-In Self-Test

Project Partner: Philips Electronics, Netherlands

09.2000 - 09.2003, Philips-Project    

MMU for Leon

Project page: MMU for Leon

Project Partner: Gaisler Research, Sweden

12.2002 - 03.2003, Gaisler Research-Project    

DAAD Project - ASTRO: Advanced Functional Built-In Self-Test Architectures for System-on-Chip

Project page: Advanced Functional Built-In Self-Test Architectures for System-on-Chip

Partner: University of Turin

01.2000 - 12.2002, DAAD/Vigoni-Project    

EuNICE: European Network for Initial and Continuing Education in VLSI/SoC Testing using remote ATE facilities

Project page: European Network for Initial and Continuing Education in VLSI/SoC Testing using remote ATE facilities

Partners: Universities of Montpellier, Barcelona, Turin, Lubljana and, as industrial partener, Agilent Technologies

 

09.2001 - 07.2004, ESPRIT-Project    

BMBF Projekt: Functional Built-In Self-Test

Project page: Functional Built-In Self-Test

Partners: Universities of Tallin and Dresden

01.1999 - 03.2003, BMBF-Project    

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