Books and Book Chapters

@inbook{Wunderlich2023,
  author = {Wunderlich, Hans-Joachim},
  editor = {Girard, Patrick and Blanton, Shawn and Wang, Li-C.},
  title = {{Machine Learning Support for Logic Diagnosis and Defect Classification}},
  booktitle = {Machine Learning Support for Fault Diagnosis of System-on-Chip },
  publisher = {Springer International Publishing},
  year = {2023},
  pages = {99--133},
  abstract = {Innovative manufacturing processes allow the integration of billions of transistors into a single chip, and the implementation of extremely dense designs, but they also come with increased variability and new reliability threats. Both, new processes and more complex designs introduce a higher degree of indeterminism which challenges logic diagnosis and defect classification. Design techniques like selective hardening, fault masking, and error masking or adaptive voltage and frequency scaling (AVFS) increase reliability, but make test, diagnosis, and defect classification even more difficult. This chapter presents machine learning techniques for distinguishing variations from reliability threats due to defects, for identifying different defect types during diagnosis, and for distinguishing transient errors covered by hardening or masking from intermittent faults.},
  url = {https://doi.org/10.1007/978-3-031-19639-3_4},
  doi = {http://dx.doi.org/10.1007/978-3-031-19639-3_4}
}

@inbook{doi:10.3139/9783446470453.009,
  author = {Wunderlich, Hans-Joachim},
  editor = {Siemers, Christian and Sikora, Axel},
  title = {{Test und Diagnose}},
  booktitle = {Taschenbuch Digitaltechnik},
  publisher = {Carl Hanser Verlag GmbH & Co. KG},
  year = {2022},
  pages = {266-289},
  edition = {4. neu bearbeitete Auflage},
  url = {https://www.hanser-elibrary.com/doi/abs/10.3139/9783446470453.009},
  doi = {http://dx.doi.org/10.3139/9783446470453.009}
}

@inbook{BauerZKSWH2021,
  author = {Bauer, Lars and Zhang, Hongyan and Kochte, Michael A. and Schneider, Eric and Wunderlich, Hans-Joachim and Henkel, Jörg},
  editor = {Henkel, Jörg and Dutt, Nikil},
  title = {{Online Test Strategies and Optimizations for Reliable Reconfigurable Architectures}},
  booktitle = {Dependable Embedded Systems},
  publisher = {Springer International Publishing},
  year = {2021},
  pages = {277--302},
  abstract = {Runtime/reconfigurable architectures based on Field-Programmable Gate Arrays (FPGAs) are a promising augment to conventional processor architectures such as Central Processing Units (CPUs) and Graphic Processing Units (GPUs). Since the reconfigurable parts are typically manufactured in the latest technology, they may suffer from aging and environmentally induced dependability threats. In this chapter, strategic online test methods for dependable runtime-reconfigurable architectures as well as cross-layer optimizations for high reliability and lifetime are developed. Firstly, two orthogonal online tests are proposed that ensure reliable configuration of the reconfigurable fabric and aid fault detection. Secondly, a novel design method called module diversification is presented that enables self-repair of the system in case of faults caused by degradation effects as well as single-event upsets in the configuration. Thirdly, a novel stress-aware placement method is proposed that aims for slowing down system degradation by aging effects. The combined methods ensure reliable operation across architectural and gate level and allow to prolong the lifetime of dependable runtime-reconfigurable architectures.},
  url = {https://doi.org/10.1007/978-3-030-52017-5_12},
  doi = {http://dx.doi.org/10.1007/978-3-030-52017-5_12}
}

@inbook{BauerZKSWH2019,
  author = {Bauer, Lars and Zhang, Hongyan and Kochte, Michael A. and Schneider, Eric and Wunderlich, Hans-Joachim. and Henkel, Jörg},
  editor = {Al-Hashimi, B. M. and Merrett, G. V.},
  title = {{Advances in Hardware Reliability of Reconfigurable Many-core Embedded Systems}},
  booktitle = {Many-Core Computing: Hardware and software},
  publisher = {Institution of Engineering and Technology (IET)},
  year = {2019},
  pages = {395--416},
  url = {https://www2.theiet.org/resources/books/computing/many-core-comp.cfm}
}

@inbook{Wunde2014,
  author = {Wunderlich, Hans-Joachim},
  editor = {Siemers, Christian and Sikora, Axel},
  title = {{Test und Diagnose}},
  booktitle = {Taschenbuch Digitaltechnik},
  publisher = {Carl Hanser Verlag GmbH & Co. KG},
  year = {2014},
  pages = {262--285},
  edition = {3. neu bearbeitete Auflage},
  url = {http://www.hanser-elibrary.com/isbn/9783446432635}
}

@inbook{GirarW2010,
  author = {Girard, Patrick and Wunderlich, Hans-Joachim},
  editor = {Wunderlich, Hans-Joachim},
  title = {{Models for Power-Aware Testing}},
  booktitle = {Models in Hardware Testing},
  publisher = {Springer-Verlag Heidelberg},
  year = {2010},
  volume = {43},
  pages = {187--215},
  keywords = {Low power test; Design for test},
  abstract = {Power consumption of circuits and systems receives more and more attention. In test mode, power consumption is even more critical than in system model and has severe impact on reliability, yield and test costs. This chapter describes the different types and sources of test power. Power-aware techniques for test pattern generation, design for test and test data compression are presented which allow efficient power constrained testing with minimized hardware cost and test application time.},
  doi = {http://dx.doi.org/10.1007/978-90-481-3282-9_7}
}

@book{Wunde2009,
  editor = {Wunderlich, Hans-Joachim},
  title = {{Models in Hardware Testing}},
  publisher = {Springer-Verlag Heidelberg},
  year = {2010},
  volume = {43},
  keywords = {Diagnosis; Fault modeling; Memory test; Test of digital systems},
  abstract = {Model based testing is the most powerful technique for testing hardware and software systems. Models in Hardware Testing describes the use of models at all the levels of hardware testing. The relevant fault models for nanoscaled CMOS technology are introduced, and their implications on fault simulation, automatic test pattern generation, fault diagnosis, memory testing and power aware testing are discussed. Models and the corresponding algorithms are considered with respect to the most recent state of the art, and they are put into a historical context by a concluding chapter on the use of physical fault models in fault tolerance.
Models in Hardware Testing treats models and especially fault models in hardware testing in a comprehensive way not found anywhere else. Engineers who are responsible for product quality and test coverage, students who want to learn about quality assessment for new technologies or lecturers who are interested in the most recent advances in model based hardware testing will take benefits from reading.
The material collected in Models in Hardware Testing was prepared for the forum in honor of Christian Landrault in connection with the European Test Symposium 2009.},
  url = {http://www.springer.com/engineering/circuits+&+systems/book/978-90-481-3281-2},
  doi = {http://dx.doi.org/10.1007/978-90-481-3282-9}
}

@inbook{WundeH2009,
  author = {Wunderlich, Hans-Joachim and Holst, Stefan},
  editor = {Wunderlich, Hans-Joachim},
  title = {{Generalized Fault Modeling for Logic Diagnosis}},
  booktitle = {Models in Hardware Testing},
  publisher = {Springer-Verlag Heidelberg},
  year = {2010},
  volume = {43},
  pages = {133--155},
  keywords = {Logic diagnosis; Fault models},
  abstract = {To cope with the numerous defect mechanisms in nanoelectronic technology, more and more complex fault models have been introduced. Each model comes with its own properties and algorithms for test generation and logic diagnosis. In diagnosis, however, the defect mechanisms of a failing device are not known in advance, and algorithms that assume a specific fault model may fail. Therefore, diagnosis techniques have been proposed that relax fault assumptions or even work without any fault model. In this chapter, we establish a generalized fault modeling technique and notation. Based on this notation, we describe and classify existing models and investigate the properties of a fault model independent diagnosis technique.},
  doi = {http://dx.doi.org/10.1007/978-90-481-3282-9_5}
}

@inbook{WundeZ2010,
  author = {Wunderlich, Hans-Joachim and Zöllin, Christian},
  editor = {Girard, Patrick and Nicolici, Nicola and Wen, Xiaoqing},
  title = {{Power-Aware Design-for-Test}},
  booktitle = {Power-Aware Testing and Test Strategies for Low Power Devices},
  publisher = {Springer-Verlag Heidelberg},
  year = {2010},
  pages = {117--146},
  abstract = {This chapter describes Design-for-Test (DfT) techniques that allow for controlling the power consumption and reduce the overall energy consumed during a test. While some of the techniques described elsewhere in this book may also involve special DfT, the topics discussed here are orthogonal to those techniques and may be implemented independently.},
  doi = {http://dx.doi.org/10.1007/978-1-4419-0928-2_4}
}

@book{BertsGJSW2009,
  editor = {Bertsche, Bernd and Göhner, Peter and Jensen, Uwe and Schinköthe, Wolfgang and Wunderlich, Hans-Joachim},
  title = {{Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertung in frühen Entwicklungsphasen}},
  publisher = {Springer-Verlag Heidelberg},
  year = {2009},
  keywords = {Mechatronik; Method; komplexe Systeme},
  abstract = {- Ganzheitliche Zuverlässigkeitsbetrachtung in frühen Entwicklungsphasen für mechatronische Komponenten bisher kaum verfügbar
- Sicherheitsrelevante Bauteile betroffen
- Mechatronische Komponenten sind in der Praxis immer noch relativ störungsanfällig
- Mit zahlreichen detaillierten Abbildungen
Von mechatronischen Systemen wird heutzutage trotz der Funktionalitäts- und Leistungsfähigkeitszunahme insbesondere auch eine erhöhte Zuverlässigkeit erwartet. Die Zuverlässigkeit sollte dabei so früh wie möglich in den Entwicklungsprozess miteinbezogen werden, da in dieser Phase die grundlegenden Entscheidungen über das System getroffen werden. Aus diesem Grund thematisiert dieses Buch die Zuverlässigkeitsbewertung mechatronischer Systeme – speziell in frühen Entwicklungsphasen. Herausforderungen hierbei sind vor allem die ganzheitliche Betrachtung über die Domänen Mechanik, Elektronik und Software sowie unsichere bzw. unvollständige Daten. Neben der domänenübergreifenden Betrachtungsweise werden zudem Themenaspekte in den einzelnen Domänen vertieft, die zur Zuverlässigkeitsbewertung in frühen Entwicklungsphasen dienen.
Inhalt im Detail
- Grundlagen
- Methodik zur Zuverlässigkeitsbewertung mechatronischer Systeme
- Mathematische Modelle zur quantitativen Analyse der Zuverlässigkeit
- Zuverlässigkeitsbetrachtung mechanischer Systemumfänge
- Systemzuverlässigkeit am Beispiel feinwerktechnischer Systeme
- Zuverlässigkeit der Software
- Bewertung und Verbesserung der Zuverlässigkeit von mikroelektronischen Komponenten},
  url = {http://www.springer.com/engineering/mechanical+eng/book/978-3-540-85089-2},
  doi = {http://dx.doi.org/10.1007/978-3-540-85091-5}
}

@inbook{WundeEK2009,
  author = {Wunderlich, Hans-Joachim and Elm, Melanie and Kochte, Michael A.},
  editor = {Bertsche, Bernd and Göhner, Peter and Jensen, Uwe and Schinköthe, Wolfgang and Wunderlich, Hans-Joachim},
  title = {{Bewertung und Verbesserung der Zuverlässigkeit von mikroelektronischen Komponenten in mechatronischen Systemen}},
  booktitle = {Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertung in frühen Entwicklungsphasen},
  publisher = {Springer-Verlag Heidelberg},
  year = {2009},
  pages = {391--464},
  abstract = {In den letzten Jahrzehnten hat der Anteil der informationsverarbeitenden Komponenten an den Herstellungskosten mechatronischer Systeme rapide zugenommen. In den 70er Jahren machte die Informationsverarbeitung noch ca. 15% des Systems aus. Zu Beginn dieses Jahrtausends sind es bereits über 60% [8.9], wie auch aus Abb. 8.1 hervorgeht. Dieser Zuwachs in den Herstellungskosten ist auf die Zunahme der durch die Informationsverarbeitung realisierten Funktionen zurückzuführen. Sehr deutlich ist diese Zunahme im Automobil zu beobachten. Während das Antiblockiersystem und die digitale Motorsteuerung schon seit Jahren zum Standard gehören, werden nun zunehmend auch Fahrerassistenz- und Infotainmentsysteme ins Kraftfahrzeug integriert. Bei diesen Systemen beginnt die Grenze zwischen klassischer Sicherheits- und Komfortfunktion zu verschwimmen. Die Bandbreite möglichen Fehlverhaltens reicht vom Ausfall des Navigationssystems über Störungen der Zentralverriegelung bis hin zum automatischen Einleiten von Bremsmanövern bei hohen Geschwindigkeiten. Entsprechend ergeben sich hier hohe Anforderungen an die Zuverlässigkeit dieser Systeme.},
  doi = {http://dx.doi.org/10.1007/978-3-540-85091-5_8}
}

@inbook{Wunde2007,
  author = {Wunderlich, Hans-Joachim},
  editor = {Siemers, Christian and Sikora, Axel},
  title = {{Test und Diagnose}},
  booktitle = {Taschenbuch Digitaltechnik},
  publisher = {Fachbuchverlag Leipzig im Carl Hanser Verlag},
  year = {2007},
  pages = {267--290},
  edition = {2. Auflage}
}

@inbook{HelleWH1998,
  author = {Hellebrand, Sybille and Wunderlich, Hans-Joachim and Hertwig, Andre},
  editor = {Nicolaidis, Michael and Zorian, Yervant and Pradhan, Dhiraj K.},
  title = {{Mixed-Mode BIST Using Embedded Processors}},
  booktitle = {On-Line Testing for VLSI},
  publisher = {Kluwer Academic Publishers},
  year = {1998},
  volume = {11},
  keywords = {Circuits & Systems; Electronics & Electrical Engineering; Information Systems and Applications},
  url = {http://www.springer.com/engineering/circuits+%26+systems/book/978-0-7923-8132-7}
}

@inbook{Wunde1998,
  author = {Wunderlich, Hans-Joachim},
  editor = {Börger, Egon},
  title = {{Test and Testable Design}},
  booktitle = {Architecture Design and Validation Methods},
  publisher = {Springer-Verlag Heidelberg},
  year = {1998},
  pages = {141--190},
  abstract = {Defects may occur during the fabrication process and during the lifetime of integrated circuits. Integrating a faulty device into systems will result in expensive repairs or even in unsafe situations and should be avoided by testing the chips.
This section explains defect mechanisms and their consequences for the product quality. Methods for test pattern generation are discussed, and it is shown how these methods can already be supported in the design phase. Modern systems-on- chip often have the capabilites of testing themselves, and recent built-in self-test techniques (BIST) are presented.},
  url = {http://dl.acm.org/citation.cfm?id=357915.357924}
}

@book{Helle1991,
  editor = {Hellebrand, Sybille},
  title = {{Synthese vollständig testbarer Schaltungen}},
  publisher = {VDI Verlag Düsseldorf},
  year = {1991},
  volume = {10},
  number = {177}
}

@book{Wunde1991,
  editor = {Wunderlich, Hans-Joachim},
  title = {{Hochintegrierte Schaltungen: Prüfgerechter Entwurf und Test}},
  publisher = {Springer-Verlag Heidelberg},
  year = {1991},
  abstract = {Mit dem vorliegenden Lehrbuch werden erstmalig in deutscher Sprache der prüfgerechte Entwurf und der Test hochintegrierter Schaltungen in umfassender Weise behandelt. Das Werk wendet sich an alle, die in Studium, Lehre, Forschung und Entwicklung Kenntnisse auf diesem Gebiet erwerben oder vertiefen möchten. Insbesondere erhält der Schaltungsentwickler einen Überblick über die Maßnahmen, die zur Verbesserung der Testbarkeit seiner Schaltungen beitragen können; der Entwickler von Entwurfssystemen findet zahlreiche, teilweise neue Algorithmen und Verfahren für den automatisierten Entwurf testbarer Schaltungen und für die zugehörige Testerzeugung. Die Verfahren werden in einem einheitlichen theoretischen Rahmen vorgestellt. Bei dieser einheitlichen Modellierung der Schaltung und der Algorithmen bleibt jedoch stets die Verbindung zur konkreten technischen Realisierung gewahrt.},
  url = {http://www.springer.com/computer/information+systems+and+applications/book/978-3-540-53456-3}
}

@book{Wunde1987,
  editor = {Wunderlich, Hans-Joachim},
  title = {{Probabilistische Verfahren für den Test hochintegrierter Schaltungen}},
  publisher = {Springer-Verlag Heidelberg},
  year = {1987},
  volume = {140},
  url = {http://www.springer.com/engineering/electronics/book/978-3-540-18072-2}
}