To the website of the University of Stuttgart

ROCK: Robust On-Chip communication through hierarchical online diagnosis and reconfiguration

Project description

The project ROCK targets the analysis and the prototypical development of robust architectures and associated design practices for Networks-on-Chips. Thereby, it meets the challenges of increased susceptibility of on-chip communication infrastructures against the massive influences caused by escalating integration density. ROCK pursues the strategy of conducting fault detection, online diagnosis und specific reconfiguration to tackle faults in a hierarchical manner throughout all network layers, aiming at selecting an optimal combination of activities over all layers. The quality of potential solutions is measured by their energy-minimal compliance to assurances made with respect to the performability of the network. For this purpose, performability will be defined for the research area of NoCs, incorporating communication performance and fault statistics. Any algorithms and architectures for controlling and performing diagnosis and reconfiguration shall themselves be designed as fault tolerant. Furthermore, their operation shall be transparent to the application processes and minimize interference with regular NoC communication. A wide range of architectures will be investigated based on the enabling technology of NoC fault models and high-level NoC fault simulation.

 

Publications

 

    Journal and conference contributions
    • Schley, G.; Radetzki, M.:
      Schichtenübergreifende Fehlertoleranz in On-Chip Verbindungsnetzwerken
      In Proceedings Zuverlässigkeit und Entwurf (ZuE'13)
    • Eggenberger, M.; Radetzki, M.:
      Fine Grained Adaptive Simulation with Application to NoCs.
      In Proceedings Forum on Design Languages (FDL'13)
    • Xu T.; Schley G.; Liljeberg P.; Radetzki M.; Plosila J.; Tenhunen H.:
      Optimal placement of vertical connections in 3D Network-on-Chip
      Journal of Systems Architecture, Volume 59, Issue 7, 2013
    • Eggenberger, M.; Radetzki, M.:
      Scalable Parallel Simulation of Networks on Chip
      In Proceedings 7th International Symposium on Networks-on-Chip (NOCS'13)
    • Schley, G.; Batzolis, N.; Radetzki, M.:
      Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip
      In Proceedings EUROMICRO Conference on Parallel, Distributed and Network-Based Processing (PDP'13)
    Workshop contributions

 

Project partner

 

Contact

Akzeptieren

Diese Webseite verwendet Cookies. Durch die Nutzung dieser Webseite erklären Sie sich damit einverstanden, dass Cookies gesetzt werden. Mehr erfahren, zum Datenschutz