Publikationen

2019

• Strobel, M.; Radetzki, M.: A Backend Tool for the Integration of Memory Optimizations into Embedded Software. Proc. Forum on Specification & Design Languages (FDL), Southampton, 2019 (accepted for publication).

• Rudolf, J.; Strobel, M.; Benz, J.; Haubelt, C.; Radetzki, M.; Bringmann, O.: Automated Sensor Firmware Development - Generation, Optimization, and Analysis. Proc. the 22nd Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Kaiserslautern, 2019.

2018

• Hou, J.; Radetzki, M.: Performability Analysis of Mesh-based NoCs Using Markov Reward Model. Proc. 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP), Cambridge (UK), 2018.

2017

• Gil, L.; Radetzki, M.: Semi-symbolic operational computation for robust control system design. Proc. 22nd International Conference on Methods and Models in Automation and Robotics (MMAR), Midzyzdroje (PL), 2017.

• Strobel, M.; Radetzki, M.: Hybrid Instruction Set Simulation for Fast and Accurate Memory Access Profiling. Proc. 13th International Workshop on Intelligent Solutions in Embedded Systems (WISES), Hamburg, 2017.

• Schley, G.; Dalirsani, A.; Eggenberger, M.; Hatami, N.; Wunderlich, H.-J.; Radetzki, M.: Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. IEEE Transactions on Computers, vol. 66, no. 5, 2017.

2016

• Gil, L.; Radetzki, M.: Optimized Disturbance Weighting for Robust System Design under Parameter Uncertainties. Proc. 15th ITG/GMM-Symposium ANALOG, 2016.

• Strobel, M.; Eggenberger, M.; Radetzki, M.: Low Power Memory Allocation and Mapping for Area-Constrained Systems-On-Chips. EURASIP Journal on Embedded Systems, 2016.

• Schley, G.; Ahmed, I.; Afzal, M.; Radetzki, M.: Reconfigurable fault tolerant routing for networks-on-chip with logical hierarchy. Computers & Electrical Engineering 51 (2016), pp. 195–206.

• Gil, L.; Radetzki, M.: Orthogonal Signal Modeling and Operational Computation of AMS Circuits for Fast and Accurate System Simulation.  Proc. Design Automation and Test in Europe (DATE), Dresden, 2016.

• Eggenberger, M.; Strobel, M.; Radetzki, M.: Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures. Proc. 24th Euromicro International Conference on Parallel, Distributed and Network-based Processing, Heraklion, 2016.

2015

• Gil, L.; Radetzki, M.: SystemC AMS Power Electronic Modelling with Ideal Instantaneous Switches. In: Oppenheimer, F.; Medina, M. (Eds.): Languages, Design Methods, and Tools for Electronic System Design, Lecture Notes in Electrical Engineering, vol. 361, pp. 181-205, Springer, 2015.

• Eggenberger, M.; Radetzki, M.: Optimal Memory Selection for Low Power Embedded Systems. Proc. 12th International Workshop on Intelligent Solutions in Embedded Systems (WISES), Ancona, 2015. Best paper award.

• Wunderlich, H.J.; Radetzki, M.: Multi-Layer Test and Diagnosis for Dependable NoCs. Proc. 9th International Symposium on Networks-on-Chip (NOCS), Vancouver, 2015.

• Schley, G.; Radetzki, M.: Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip. Proc. 23rd Euromicro International Conference on Parallel, Distributed and Network-based Processing, Turku, 2015.

2014

• Dalirsani, A.; Hatami, N.; Imhof, M.E.; Eggenberger, M.; Schley, G.; Radetzki, M.; Wunderlich, H.-J.: On Covering Structural Defects in NoCs by Functional Tests. In Proc. of the 23rd IEEE Asian Test Symposium (ATS'14), Hangzhou, China, 16-19 November 2014

• Gil, L.; Radetzki, M.: SystemC-AMS Power Electronic Modeling with Ideal Instantaneous Switches.Proc. Forum on Design Languages (FDL), Munich, 2014.

• Haetzer, B.; Radetzki, M.: Comparison of Parallel SystemC Simulation Approaches at RTL. Proc. Forum on Design Languages (FDL), Munich, 2014.

• Haetzer, B.; Radetzki, M.: SystemC Modeling with Transaction Events. In Louërat, M.M.; Maehne, T. (Eds.): Languages, Design Methods, and Tools for Electronic System Design, Lecture Notes in Electrical Engineering, vol. 311, Springer, 2014.

• Eggenberger, M.; Radetzki, M.: Fine-Grained Adaptive Simulation. In Louërat, M.M.; Maehne, T. (Eds.): Languages, Design Methods, and Tools for Electronic System Design, Lecture Notes in Electrical Engineering, vol. 311, Springer, 2014.

• Haetzer, B.; Radetzki, M.: Asynchronous Parallel Simulation with Transaction Events.  Proc. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, 2014.

2013

• Radetzki, M.; Feng, C.; Zhao, X.; Jantsch, A.: Methods for Fault Tolerance in Networks on Chip. ACM Computing Surveys, vol. 46, no. 1, article 8, October 2013

• Schley, G.; Radetzki, M.: Schichtenübergreifende Fehlertoleranz in On-Chip Verbindungsnetzwerken. Proc. Zuverlässigkeit und Entwurf (ZuE), Dresden, 2013.

• Eggenberger, M.; Radetzki, M.: Fine Grained Adaptive Simulation with Application to NoCs. Proc. Forum on Design Languages (FDL), Paris, 2013.

• Haetzer, B.; Radetzki, M.: SystemC Transaction Level Modeling with Transaction Events. Proc. Forum on Design Languages (FDL), Paris, 2013. Best paper award.

• Kohler, A.; Radetzki, M.: Power Management for High-Performance Applications on Network-on-Chip-based Multiprocessors. Proc. IEEE International Conference on Green Computing and Communications (GreenCom), Beijing, 2013.

• Xu, T.C.; Schley, G.; Liljeberg, P.; Radetzki, M.; Plosila, J.; Tenhunen, H.: Optimal placement of vertical connections in 3D Network-on-Chip. Journal of Systems Architecture, vol. 59, no. 7, August 2013, pp. 441-454.

• Latif, K.; Rahmani, A.-M.; Nigussie, E.; Seceleanu, T.; Radetzki, M.; Tenhunen, H.: Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip. Journal of Electronic Testing: Theory and Applications (JETTA), vol. 29, no. 3, June 2013, pp. 431-452.

• Eggenberger, M; Radetzki, M.: Scalable Parallel Simulation of Networks on Chip. Proc. 7th IEEE/ACM International Symposium on Networks on Chip (NOCS), Tempe/AZ, 2013. Best paper award.

•  Schley, G.; Batzolis, N.; Radetzki, M.: Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip. EUROMICRO Conference on Parallel, Distributed and Network-Based Processing (PDP), Belfast, 2013.

• Lu, W.; Radetzki, M.: Concurrent and comparative fault simulation in SystemC and its application in robustness evaluation. J. Microprocessors and Microsystems (MICPRO), vol. 37, no. 2, March 2013, pp. 115-128

2012

• Kohler, A.; Radetzki, M.: Latency-Optimized Collectives for High Performance on Intel's Single-Chip Cloud Computer. In: Lankes, S.; Clauss, C. (Eds.): Proc. Many-core Applications Research Community Symposium (MARC), Aachen, 2012.

• Lu, W.; Radetzki, M.: Systematic Fault Simulation of a Fault Tolerant NoC. Proc. edaWorkshop, Hannover, 2012.

• Kohler, A.; Radetzki, M.: Optimized Reduce for Mesh-Based NoC Multiprocessors. Proc. 2nd Workshop on Communication Architecture for Scalable Systems (CASS), Shanghai, 2012.

• Salimi Khaligh, R.; Radetzki, M.: Semantics and Efficient Simulation of Accuracy-Adaptive TLMs. J. Design Automation for Embedded Systems (DAEM), vol. 16, no. 3, pp. 1 - 29, Sept. 2012.

• Kohler, A.; Gschwandtner, P.; Radetzki, M.; Fahringer, T.: Low-Latency Collectives for the Intel SCC. Proc. IEEE Cluster, Beijing, 2012.

• Kohler, A.; Castillo-Sanchez, J.M.; Groß, J.; Radetzki, M.: Minimal MPI as Programming Interface for Multicore Systems-on-Chip. Proc. Forum on Design and Specification Languages (FDL), Vienna, 2012.

• Barke, M.; Kärgel, M.; Lu, W.; Salfelder, F.; Hedrich, L.; Olbrich, M.; Radetzki, M.; Schlichtmann, U.: Robustness Validation of Integrated Circuits and Systems. Proc. Asia Symposium on Quality Electronic Design (ASQED), Penang,

2011

• Radetzki, M.: Fault-Tolerant Differential Q Routing in Arbitrary NoC Topologies. Proc. 9th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), Melbourne, 2011.
• Haetzer, B.; Schley, G.; Salimi Kahligh, R.; Radetzki, M.: Practical Embedded Systems Engineering Syllabus for Graduate Students with Multidisciplinary Backgrounds. Proc. Workshop on Embedded Systems Education (WESE), Taipei, 2011.
  
• Lu, W.; Radetzki, M.: SystemC-Fehlersimulation auf der Systemebene mit nebenläufig-komparativen Verfahren. Proc. Zuverlässigkeit und Entwurf (ZuE), Hamburg, 2011.
• Radetzki, M.: Fehlertolerantes differentielles Q-Routing für On-Chip-Verbindungsnetzwerke mit beliebiger Topologie. Proc. Zuverlässigkeit und Entwurf (ZuE), Hamburg, 2011.
• Salimi Khaligh, R.; Radetzki, M.: A Metamodel and Semantics for Transaction Level Modeling. Proc. Forum on Design Languages (FDL), Oldenburg, 2011.
• Haetzer, B.; Radetzki, M.: A Case Study on Message-Based Discrete Event Simulation for Transaction Level Modeling. Proc. Forum on Design Languages (FDL), Oldenburg, 2011.
• Lu, W.; Radetzki, M.: Efficient Fault Simulation of SystemC Designs. Proc. EUROMICRO Conference on Digital System Design (DSD), Oulu, 2011.
• Schley, G.; Radetzki, M.: Optimal Distribution of Privileged Nodes in Networks-on-Chip. Proc. Workshop on Intelligent Solutions for Embedded Systems (WISES), Regensburg, 2011.
• Lu, W.; Metzdorf, M.; Helms, D.; Radetzki, M.; Nebel, W.: Robustness Evaluation of Embedded Software Systems. Proc. edaworkshop, Dresden, 2011.
• Radetzki, M.; Kohler, A.: Cost-based Deflection Routing for Intelligent NoC Switches. In Conti, M.; Orcioni, S.; Martinez Madrid, N.; Seepold, R.E.D. (Eds.): Solutions on Embedded Systems, Lecture Notes in Electrical Engineering, vol. 81, Springer, 2011.
• Lu, W.; Radetzki, M.: Concurrent and Comparative Fault Simulation with SystemC., 3rd Workshop on Design for Reliability (DFR'11), Heraklion, January 2011.

2010

• Radetzki, M.; Bringmann, O.; Nebel, W.; Olbrich, M.; Salfelder, F.; Schlichtmann, U.: Robustheit nanoelektronischer Schaltungen und Systeme. Zur Veröffentlichung angenommen, 4. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf, Wildbad Kreuth, September 2010.
• Salimi Khaligh, R.; Radetzki, M.: A Dynamic Load Balancing Method for Parallel Simulation of Accuracy Adaptive TLMs.  Forum on Design Languages (FDL), Southampton, September 2010.
• Schley, G.; Radetzki, M.; Kohler, A.: Degradability Enabled Routing for Network-on-Chip Switches. In Information Technology (it), vol. 52, no. 4, August 2010.
• Kohler, A.; Schley, G.; Radetzki, M.: Fault Tolerant Network on Chip Switching with Graceful Performance Degradation. In IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 20, no. 6, pp. 883-896, Juni 2010.
• Salimi Khaligh, R.; Radetzki, M.: Modelling Constructs and Kernel for Parallel Simulation of Accuracy Adaptive TLMs. Proc. Design Automation and Test in Europe (DATE), Dresden, 2010

2009

• Kohler, A.; Radetzki, M.: A SystemC TLM2 Model of Communication in Wormhole Switched Networks-on-Chip. Proc. Forum on Design Languages (FDL), Sophia Antipolis, September 2009.
• Kohler, A.; Radetzki, M.: Degradierbare Switches für fehlertolerante Networks-on-Chip. 3. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE), Stuttgart, September 2009.
• Salimi Khaligh, R.; Radetzki, M.: Efficient Parallel Transaction Level Simulation by Exploiting Temporal Decoupling. Proc. International Embedded Systems Symposium (IESS), Schloss Langenargen, September 2009.
• Radetzki, M.; Kohler, A.: An Intelligent Deflection Router for Networks-on-Chip. Proc. 7th Workshop on Intelligent Solutions in Embedded Systems (WISES), Ancona, June 2009.
• Kohler, A.; Radetzki, M.: Fault-Tolerant Architecture and Deflection Routing for Degradable NoC Switches. Proc. 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS), San Diego, May 2009.
• Radetzki, M. (Ed.): Languages for Embedded Systems and their Applications. Lecture Notes in Electrical Engineering, vol. 36, Springer.
• Salimi Khaligh, R.; Radetzki, M.: Adaptive Interconnect Models for Transaction-Level Simulation. In M. Radetzki (Ed.): Languages for Embedded Systems and their Applications, Springer.
• Kochte, M.; Zöllin, Ch.; Imhof, M.; Salimi Khaligh, R.; Radetzki, M.; Wunderlich, H.-J.; Di Carlo, S.; Prinetto, P.: Test Exploration and Validation Using Transaction Level Models. Proc. Design Automation and Test in Europe (DATE), Nice, April 2009.
• Kohler, A.; Radetzki, M.: Modellierung und Simulation von Networks-on-Chip mit OSCI TLM2. 12. Workshop Modellierung und Verifikation von Schaltungen und Systemen, Berlin, März 2009.
• Kochte, M.; Zöllin, Ch.; Imhof, M.; Salimi Khaligh, R.; Radetzki, M.; Wunderlich, H.-J.; Di Carlo, S.; Prinetto, P.: Modellierung der Testinfrastruktur auf der Transaktionsebene. 21. Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Bremen, Februar 2009.

2008

• Radetzki, M.: Fehlertoleranz in Networks-on-Chip mit Deflection Routing. Proc. 2. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf, Ingolstadt, 2008.
• Salimi Khaligh, R.; Radetzki, M.: A Latency, Preemption and Data Transfer Accurate Adaptive Transaction Level Model for Efficient Simulation of Pipelined Buses. Proc. Forum on Design Languages (FDL), Stuttgart, 2008.
• Radetzki, M.; Salimi Khaligh, R.: On Construction of Cycle-Approximate Bus TLMs. In : E. Villar (Ed.): Embedded Systems Specification and Design Languages. Springer, 2008.
• Hao, W.; Radetzki, M.: A Data Traffic Efficient H.264 Deblocking IP. Proc. International Symposium on Circuits and Systems (ISCAS), Seattle, 2008.
• Radetzki, M.; Salimi Khaligh, R.: Accuracy-Adaptive Simulation of Transaction Level Models. Proc. Design Automation and Test in Europe (DATE), Munich, 2008

2007

• Radetzki, M.; Salimi Khaligh, R.: Modelling Alternatives for Cycle Approximate Bus TLMs. Proc. Forum on Design Languages (FDL), Barcelona, 2007.
• Radetzki, M.: Object-Oriented Transaction Level Modelling. In: S. Huss (Ed.): Advances in Design and Specification Languages for Embedded Systems. Springer, 2007.
• Salimi Khaligh, R.; Radetzki, M.: Efficient and Extensible Transaction Level Modeling Based on an Object Oriented Model of Bus Transactions. In: Rettberg, A., et al. (Eds.): Embedded System Design: Topics, Techniques and Trends. Springer, 2007.
• Radetzki, M.: Modellierung mit Guarded Transactions zum robusten Entwurf von Hardware-Software-Systemen in SystemC. 1. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf, München, 2007.
• Radetzki, M.: Modellierung auf der Transaktionsebene unter Nutzung des Entwurfsmusters des aktiven Objekts. 10. Workshop Modellierung und Verifikation von Schaltungen und Systemen, Erlangen, 2007.

2006

• Radetzki, M.: SystemC TLM Transaction Modelling and Dispatch for Active Objects. Proc. Forum on Design Languages (FDL), Darmstadt, 2006.

2005 and earlier

• Brand, H.J.; Rülke, S.; Radetzki, M.: IP Qualification for Efficient System Design. Proc. International Symposium on Quality Electronic Design (ISQED), 2004.

• Schaaf, M.; Freßmann, A.; Maximini, R.; Bergmann, R.; Tartakovski, A.; Radetzki, M.: Intelligent IP Retrieval Driven by Application Requirements. Integration - The VLSI Journal, 37(4): 253-287, 2004.

• Vörg, A.; Radetzki, M.; Rosenstiel, W.: Measurement of IP Qualification Costs and Benefits. Proc. Design Automation and Test in Europe (DATE), Paris, 2004.

• Badelt, U.; Kühl, H.; Radetzki, M.: sciPROVE: C++ Based Verification Environment for IP and SoC Design. Forum on Design Languages (FDL), Frankfurt, 2003.

• Lange, H.; Radetzki, M.: IP Configuration Management with Abstract Parameterizations. IP Based SoC Design Workshop, Grenoble, 2002.

• Radetzki, M.: Qualität und Qualitätssicherung wiederverwendbarer Schaltungsbesch­reibungen. Informationstechnik und Technische Informatik (it+ti) 44 (2002) 2, pp. 99­-102.

• Saucier, G.; Ghanmi, L.; Hamdoun, M.; Pfirsch, Th.; ten Have, M.; Radetzki, M.; Neu­mann, P.: IP Transfer: A Mapping Problem. IP Based SoC Design Workshop, Grenoble, 2002.

• Saucier, G.; Ghanmi, L.; Skiba, K.; ten Have, M.; Radetzki, M.; Neumann, P.: IP Exchange Platform. Open ToolIP Workshop, MEDEA+ Design Automation Confer­ence, Stresa, 2002.

• Nebel, W.; Oppenheimer, F.; Schumacher, G.; Kabous, L.; Radetzki, M.; Putzke-Röming, W.: Object-Oriented Specification and Design of Embedded Hard Real-Time Systems. In: Ashenden, P.; Mermet, J.; Seepold, R. (Eds.): System-on-Chip Methodologies & Design Languages. Kluwer Academic Publishers, 2001.

• Seepold, R.; Martinez Madrid, N.; Vörg, A.; Rosenstiel, W.; Radetzki, M.: A Qualification Platform for Design Reuse. Proc. Int'l Symposium on Quality Electronic Design (ISQED), San Jose, 2002.

• Radetzki, M.; Neumann, P.; Haase, J.; Martinez Madrid, N.; Seepold, R.; Vörg, A.: Automated Qualification Flow for Soft IP. Proc. MEDEA+ Conference on Application-Oriented SoC Design, Veldhoven, 2001.

• Radetzki, M.: Synthesis of Digital Circuits from Object-Oriented Specifications. Dissertation, Universität Oldenburg, 2000.

• Radetzki, M.; Nebel, W.: Digital Circuit Design with Objective VHDL. In Mermet, J. (Ed.): Electronic Chips & Systems Design Languages. Kluwer Academic Publishers, 2001

• Nebel, W.; Oppenheimer, F.; Schumacher, G.; Kabous, L.; Radetzki, M.; Putzke-Röming, W.: Object-Oriented Specification and Design of Embedded Hard Real-Time Systems. Proc. 16th IFIP World Congress, Peking, 2000.

• Radetzki, M.; Nebel, W.: Synthesizing Hardware from Object-Oriented Descriptions. Proc. Forum on Design Languages (FDL), Lyon, 1999.

• Radetzki, M.: Overview of Objective VHDL Language Features. Proc. Forum on Design Languages (FDL), Lyon, 1999.

• Radetzki, M.; Nebel, W.: Synthesis of Hardware Structures from Object-Oriented Mod­els. Proc. 8th Int'l Symposium on Integrated Circuits, Devices and Systems (ISIC), Singapur, 1999.

• Radetzki, M.; Stammermann, A.; Putzke-Röming, W.; Nebel, W.: Data Type Analysis for Hardware Synthesis from Object-Oriented Models. Proc. Design, Automation and Test in Europe (DATE), Munich, 1999.

• Ashenden, P.J.; Wilsey, P.A.; Nebel, W.; Radetzki, M.; Putzke-Röming, W.; Peterson, G.D.: SUAVE and Objective VHDL: Object-Oriented Extensions to VHDL. Proc. Forum on Design Languages (FDL), Lyon, 1999.

• Ashenden, P.J.; Radetzki, M.: Comparison of SUAVE and Objective VHDL Language Features. Proc. Forum on Design Languages (FDL), Lyon, 1999.