[C119] | F. Regazzoni, C. Alippi, and I. Polian. Security: The dark side of approximate computing? Proc. Int’l Conf. on CAD, San Diego, CA, USA, 2018. (Accepted) |
[C118] | B. Karp, M. Gay, O. Keren, and I. Polian. Security-oriented code-based architectures for mitigating fault attacks. Proc. Conf. Design of Circuits and Integrated Systems, Lyon, F, 2018. (Accepted) |
[C117] | F. Regazzoni, A. Fowler, and I. Polian. Quantum era challenges for classical computers. Proc. Int’l Conf. Embedded Computer Systems: Architectures, Modeling and Simulation, Samos, GR, 2018. (Invited) |
[C116] | J. Burchard, M. Gay, A.-S. Messeng Ekossono, J. Horacek, B. Becker, T. Schubert, M. Kreuzer, and I. Polian. AutoFault: towards automatic construction of algebraic fault attacks. Proc. Workshop on Fault Diagnosis and Tolerance in Cryptography, Taipeh, TW, pages 65–72, 2017. (ISBN: 978-1-5386-2948-2) |
[C115] | I. Polian, F. Regazzoni, and J. Sepulveda. Introduction to hardware-oriented security for MPSoCs. Proc. IEEE Int’l System-on-Chip Conf., Munich, D, pages 102–107, 2017. (Invited; ISBN: 978-1-5386-4034-0) |
[C114] | F. Neugebauer, I. Polian, and J. Hayes. Building a better random number generator for stochastic computing. Proc. Euromicro Conf. on Digital System Design, Vienna, A, 2017. (ISBN: 978-1-5386-2146-2) |
[C113] | J. Burchard, A.-S. Messeng Ekossono, J. Horacek, M. Gay, B. Becker, T. Schubert, M. Kreuzer, and I. Polian. Towards mixed structural-functional models for algebraic fault attacks on ciphers. Proc. Int’l Veri?cation and Security Workshop, pages 7–12, Thessaloniki, GR, 2017. (ISBN: 978-1-5386-1708-3) |
[C112] | I. Polian and F. Regazzoni. Counteracting malicious faults in cryptographic circuits. Proc. IEEE European Test Symp., Limassol, CY, 2017. (Invited, ISBN: 978-1-5090-5457-2) |
[C111] | F. Neugebauer, I. Polian, and J. Hayes. Framework for quantifying and managing accu- racy in stochastic circuit design. Proc. Design, Automation and Test in Europe, Lausanne, CH, pages 1–6, 2017. (ISBN: 978-3-9815370-8-6) |
[C110] | M. Sauer, P. Raiola, L. Feiten, B. Becker, U. Rührmair, and I. Polian. Sensitized Path PUF: A lightweight embedded physical unclonable function. Proc. Design, Automation and Test in Europe, Lausanne, CH, pages 680–685, 2017. (ISBN: 978-3-9815370-8-6) |
[C109] | J. Kinseher, L. Heiss, and I. Polian. Analyzing the effects of peripheral circuit aging of embedded SRAM architectures. Proc. Design, Automation and Test in Europe, Lausanne, CH, pages 852–857, 2017. (ISBN: 978-3-9815370-8-6) |
[C108] | F. Regazzoni and I. Polian. Securing the hardware of cyber-physical systems. Proc. Asia and South Pacific Design Automation Conf., Chiba, J, pages 194–199, 2017. (Invited, ISBN: 978-1-5090-1558-0) |
[C107] | M. Sauer, J. Jiang, S. Reimer, K. Miyase, X. Wen, B. Becker, and I. Polian. On optimal power-aware path sensitization. Proc. IEEE Asian Test Symp., Hiroshima, J, pages 179–184, 2016. (ISBN: 978-1-5090-3808-4) |
[C106] | J. Burchard, M. Gay, J. Horacek, A.-S. Messeng Ekossono, T. Schubert, B. Becker, I. Po- lian, M. Kreuzer. Small scale AES toolbox: Algebraic and propositional formulas, circuit- implementations and fault equations. Proc. Conf. on Trustworthy Manufacturing and Uti- lization of Secure Devices, Barcelona, ES, 2016. |
[C105] | V. Tomashevich and I. Polian. Memory error resilient detection for massive MIMO sys- tems. Proc. European Signal Processing Conf., Budapest, H, pages 1623–1627, 2016. (ISBN: 978-0-9928-6265-7) |
[C104] | I. Polian. Security aspects of analog and mixed-signal circuits. Proc. IEEE Mixed-Signal Testing Workshop, Sant Feliu de Guixols, ES, 2016. (Invited, ISBN: 978-1-5090-2751-4) |
[C103] | J. Kinseher, M. Voelker, L. Zordan, and I. Polian. Failure mechanisms and test methods for the SRAM TVC write-assist technique. Proc. IEEE European Test Symp., Amsterdam, NL, 2016. (ISBN: 978-1-4673-9659-2) |
[C102] | V. Tomashevich and I. Polian. Detection performance of MIMO unique word OFDM. Proc. Int’l ITG Workshop on Smart Antennas, Munich, D, 2016 (ISBN: 978-3-8007-4177-9). |
[C101] | J. Kinseher, L. Zordan, I. Polian, and A. Leininger. Improving SRAM test quality by leveraging self-timed circuits. Proc. Design, Automation and Test in Europe, Dresden, D, pages 984–989, 2016. (ISBN: 978-3-9815370-6-2) |
[C100] | J. Kinseher, L. Zordan, and I. Polian. On the use of assist circuits for improved coupling fault detection in SRAMs. Proc. IEEE Asian Test Symp., Mumbai, IN, pages 61–66, 2015. (ISBN: 978-1-4673-9739-1) |
[C99] | I. Polian and A. G. Fowler. Design automation challenges for scalable quantum computing. Proc. ACM/IEEE Design Automation Conf., San Francisco, USA 2015 (Invited, ISBN: 978- 1-4503-3520-1/15/06). |
[C98] | J. Kinseher, M. Richter, and I. Polian. On the automated verification of user-defined MBIST algorithms. Proc. GMM/GI/ITG Reliability and Design Conf., Siegen, D, 2015. (ISBN: 978-3-8007-4071-0) |
[C97] | A. Paler, I. Polian, K. Nemoto, and S. Devitt. A fully fault-tolerant representation of quantum circuits. Proc. Conf. on Reversible Computation, Grenoble, F, 2015. (LNCS 9138, ISBN: 978-3-319-20860-2) |
[C96] | P. Jovanovic and I. Polian. Fault-based attacks on the Bel-T block cipher family. Proc. De- sign, Automation and Test in Europe, Grenoble, F, 2015. (ISBN: 978-3-9815-3704-8) |
[C95] | R. Kumar, P. Jovanovic, W. Burleson, and I. Polian. Parametric Trojans for fault-injection attacks on cryptographic hardware. Proc. Fault Diagnosis and Tolerance in Cryptography, Busan, KR, pages 18–28, 2014. (ISBN: 978-1-4799-6292-1) |
[C94] | V. Tomashevich, Y. Neumeier, R. Kumar, O. Keren, and I. Polian. Protecting crypto- graphic hardware against malicious attacks by nonlinear robust codes. Proc. IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Amsterdam, NL, pages 40-45, 2014. (ISBN: 978-1-4799-6155-9) |
[C93] | V. Tomashevich, C. Gimmler, N. Wehn, and I. Polian. Reliability analysis of MIMO channel preprocessing by fault injection. Proc. IEEE Int’l Conf. on Wireless for Space and Extreme Environments, Noordwijk, NL, 2014. (ISBN: 978-1-4-4799-5653-1) |
[C92] | R. Kumar, P. Jovanovic, and I. Polian. Precise fault injections using voltage and temper- ature manipulation for differential cryptanalysis Proc. IEEE On-Line Test Symp., Platja d’Aro, E, pages 43–38, 2014. (ISBN: 978-1-4799-5323-3) |
[C91] | A. Paler, S. Devitt, K. Nemoto, and I. Polian. Cross-level validation of topological quantum circuits. Proc. Conf. on Reversible Computation, Kyoto, J, pages 189–200, 2014. (LNCS 8507, ISBN 978-3-319-08494-7) |
[C90] | I. Polian, J. Jiang, and A. Singh. Detection conditions for errors in self-adaptive better- than-worst-case designs. Proc. IEEE European Test Symp., Paderborn, D, 2014. (ISBN: 978-1-4799-3415-7) |
[C89] | M. Sauer, I. Polian, M. Imhof, A. Mumtaz, E. Schneider, A. Czutro, H.-J. Wunderlich, and B. Becker. Variation-aware deterministic ATPG. Proc. IEEE European Test Symp., Paderborn, D, 2014. (ISBN: 978-1-4799-3415-7) Best Paper Award |
[C88] | V. Tomashevich, C. Gimmler, C. Fesl, N. Wehn, and I. Polian. A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systems. Proc. IEEE Symp. on Design and Diagnostics of Electronic Circuits and Systems, Warsaw, PL, pages 246–249, 2014. (Poster, ISBN: 978-1-4799-4560-3) |
[C87] | A. Paler, S. Devitt, K. Nemoto, and I. Polian. Software-based Pauli tracking in fault- tolerant quantum circuits. Proc. Design, Automation and Test in Europe, Dresden, D, 2014. (ISBN: 978-3-9815370-2-4, Interactive Presentation) |
[C86] | R. K. Uppu, R. T. Uppu, A. Singh, and I. Polian. Better-than-worst-case timing design with latch buffers on short paths. Proc. VLSI Design Conf., Mumbai, IN, pages 133–138, 2014. (ISSN: 1063-9667) |
[C85] | A. Czutro, I. Polian, S. M. Reddy, and B. Becker. SAT-based test pattern generation with improved dynamic compaction. Proc. VLSI Design Conf., pages 56–61, Mumbai, IN, 2014. (ISSN: 1063-9667) |
[C84] | J. Jiang, M. Comte, M. Aparicio Rodriguez, F. Azais, M. Renovell, and I. Polian. MIRID: Mixed-mode IR-drop Induced Delay simulator. Proc. IEEE Asian Test Symp., Yilan, Tai- wan, pages 177–182, 2013. (ISBN: 1081-7735) |
[C83] | A. Paler, I. Polian, J. Kinseher, and J.P. Hayes. Approximate simulation of circuits with probabilistic behavior. Proc. IEEE Symp. Defect and Fault Tolerance in VLSI and Nan- otechnology Systems, New York, USA, pages 95–100, 2013. (ISBN: 978-1-4799-1583-5) |
[C82] | M. Sauer, S. Reimer, T. Schubert, I. Polian, and B. Becker. Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. Proc. Design, Automation and Test in Europe, Grenoble, F, pages 448–453, 2013 (ISBN: 978-1-4673-5071-6). |
[C81] | M. Sauer, S. Reimer, I. Polian, T. Schubert, and B. Becker. Provably optimal test cube generation using Quantified Boolean Formula solving. Proc. Asia and South Pacific Design Automation Conf., Yokohama, J, pages 533–539, 2013. (ISBN: 978-1-4673-3029-9) Nomi- nated for Best Paper Award |
[C80] | A. Czutro, M.E. Imhof, J. Jiang, A. Mumtaz, M. Sauer, B. Becker, I. Polian, and H.-J. Wunderlich.Variation-aware fault grading Proc. IEEE Asian Test Symp., Niigata, J, pages 344–349, 2012. (ISBN: 978-0-7695-4876-0) |
[C79] | M. Sauer, A. Czutro, I. Polian, and B. Becker. Small-delay-fault ATPG with waveform accuracy. Proc. IEEE/ACM Int’l Conf. on CAD, San Jose, CA, USA, pages 30–36, 2012. (ISBN: 978-1-4577-1398-9) |
[C78] | A. Paler, S. Devitt, K. Nemoto, and I. Polian. Synthesis of topological quantum circuits. Proc. IEEE/ACM Int’l Symp. on Nanoscale Architectures, Amsterdam, NL, pages 181–187, 2012. (ISBN: 978-1-4503-1671-2) |
[C77] | M. Aparicio Rodriguez, M. Comte, F. Azais, Y. Bertrand, M. Renovell, J. Jiang, I. Polian, and B. Becker. An IR-drop simulation principle oriented to delay testing. Proc. Design of Circuits and Integrated Systems Conf., Avignon, F, 2012. |
[C76] | L. Feiten, M. Sauer, T. Schubert, A. Czutro, E. Boehl, I. Polian, and B. Becker. #SAT- based vulnerability analysis of security components – A case study. Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Austin, TX, USA, pages 49–54, 2012. (ISBN: 978-1-4673-3043-5) |
[C75] | M. Sauer, S. Kupferschmidt, A. Czutro, I. Polian, S. Reddy, and B. Becker. Functional test of small-delay faults using SAT and Craig interpolation. Proc. Int’l Test Conf., Anaheim, CA, USA, paper 6.3, 2012. (ISBN: 978-1-4673-1595-1) |
[C74] | V. Tomashevich, S. Srinivasan, F. Foerg, and I. Polian. Cross-level protection of circuits against faults and malicious attacks Proc. IEEE Int’l On-Line Test Symp., Sitges, E, pages 150–155, 2012. (ISBN: 978-1-4673-2082-5) |
[C73] | P. Jovanovic, M. Kreuzer, and I. Polian. A fault attack on the LED block cipher. Proc. Int’l Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE), Darm- stadt, D, pages 120–134, 2012. (LNCS 7275, ISBN: 978-3-642-29911-7) |
[C72] | M. Sauer, A. Czutro, B. Becker, and I. Polian. On the quality of test vectors for post-silicon characterization. Proc. IEEE European Test Symp., Annecy, F, 2012. (ISBN: 978-1-4673- 0696-6) |
[C71] | A. Czutro, M. Sauer, I. Polian, and B. Becker. Multi-conditional SAT-ATPG for power- droop testing. Proc. IEEE European Test Symp., Annecy, F, 2012. (ISBN: 978-1-4673-0696-6) |
[C70] | A. Czutro, M. Sauer, T. Schubert, I. Polian, and B. Becker. SAT-ATPG using preferences for improved detection of complex defect mechanisms. Proc. IEEE VLSI Test Symp., Maui, HI, USA, pages 170–175, 2012. (ISBN: 978-1-4673-1073-4) |
[C69] | J. Jiang, M. Sauer, A. Czutro, B. Becker, and I. Polian. On the optimality of K longest path generation algorithm under memory limitations. Proc. Design, Automation and Test in Europe, Dresden, D, pages 418–423, 2012. (ISBN: 978-3-9810801-8-6) |
[C68] | A. Paler, I. Polian, and J.P. Hayes. Detection and diagnosis of faulty quantum circuits. Proc. Asia and South Pacific Design Automation Conf., Sydney, AUS, pages 181–186, 2012. (ISBN: 978-1-4673-0772-7) |
[C67] | M. Sauer, J. Jiang A. Czutro, I. Polian, and B. Becker. Efficient SAT-based search for longest sensitisable paths. Proc. IEEE Asian Test Symp., New Delhi, IN, pages 108–113, 2011. (ISBN: 978-1-4577-1984-4) |
[C66] | M. Sauer, V. Tomashevich, J. Müller, M. Lewis, A. Spilla, I. Polian, B. Becker, and W. Bur- gard. An FPGA-based framework for run-time injection and analysis of soft errors in mi- croprocessors. Proc. IEEE Int’l On-Line Test Symp., Athens, GR, pages 182–185, 2011. (ISBN: 978-1-4577-1053-7) |
[C65] | M. Sauer, A. Czutro, I. Polian, and B. Becker. Estimation of component criticality in early design steps. Proc. IEEE Int’l On-Line Test Symp., Athens, GR, pages 104–110, 2011. (ISBN: 978-1-4577-1053-7) |
[C64] | A. Paler, A. Alaghi, I. Polian, and J.P. Hayes. Tomographic testing and validation of probabilistic circuits. Proc. IEEE European Test Symp., Trondheim, NO, pages 63–68, 2011. (ISBN: 978-1-4577-0483-3) |
[C63] | I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, and P. Maxwell. Towards variation- aware test methods. Proc. IEEE European Test Symp., Trondheim, NO, 2011, pages 219– 225. (ISBN: 978-1-4577-0483-3) |
[C62] | M. Sauer, A. Czutro, T. Schubert, S. Hillebrecht, I. Polian, and B. Becker. SAT-based anal- ysis of sensitisable paths. Proc. IEEE Int’l Symp. on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Cottbus, pages 93–98, 2011. (ISBN: 978-1-4244-9755-3). Best Paper Award (Test track) |
[C61] | P. Krause and I. Polian. Adaptive voltage over-scaling for resilient applications. Proc. De- sign, Automation and Test in Europe, Grenoble, F, 2011. (ISBN: 978-1-61284-208-0) |
[C60] | F. Hopsch, B. Becker, S. Hellebrand, I. Polian, V. Vermeiren, and H.-J. Wunderlich. Variation-aware fault modeling. Proc. IEEE Asian Test Symp., pages 87–93, Shanghai, China, 2010. (ISBN: 978-0-7695-4248-5) Selected for the “Best papers compendium 2002-2011” of the IEEE Asian Test Symposium. |
[C59] | I. Polian and J.P. Hayes. Modeling faults in reversible circuits. Proc. IEEE East-West Design and Test Symp., pages 376–381, St. Petersburg, Russia, 2010. (Invited) |
[C58] | B. Becker, S. Hellebrand, I. Polian, B. Straube, V. Vermeiren, and H.-J. Wunderlich. Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. Proc. Workshop on Dependable and Secure Nanocomputing, pages 95–100, Chicago, IL, USA, 2010. (ISBN: 978-1-4244-7729-6) |
[C57] | A. Czutro, I. Polian, P. Engelke, S. Reddy, and B. Becker. Dynamic compaction in SAT- based ATPG. Proc. IEEE Asian Test Symp., pages 187–190, Taichung, Taiwan, 2009. (ISBN: 978-0-7695-3864-8) |
[C56] | V. Izosimov, I. Polian, P. Pop, P. Eles, and Z. Peng. Analyse und Optimierung von fehlertoleranten eingebetteten Systemen mit gehärteten Prozessoren. Proc. GMM/GI/ITG Reliability and Design Conf., pages 79–80, Stuttgart, D, 2009. (ISBN: 978-3-8007-3178-7; poster) |
[C55] | M. Hunger, S. Hellebr /and, A. Czutro, I. Polian, and B. Becker. ATPG-based grading of strong fault-secureness. Proc. IEEE Int’l On-Line Test Symp., pages 269–274, Lisbon, PT, 2009. (ISBN: 978-1-4244-4596-7) |
[C54] | N. Houarche, M. Comte, M. Renovell, A. Czutro, P. Engelke, I. Polian, and B. Becker. An electrical model for the fault simulation of small delay faults caused by crosstalk-aggravated resistive short defects. Proc. IEEE VLSI Test Symp., pages 21–26, Santa Cruz, CA, USA, 2009. (ISBN: 978-0-7695-3598-2) |
[C53] | K.P. Ganeshpure, I. Polian, S. Kundu, and B. Becker. Reducing temperature variability by routing heat pipes. Proc. ACM Great Lakes Symp. on VLSI , Boston, MA, USA, pages 63–68, 2009. (ISBN: 978-1-60558-522-2). |
[C52] | V. Izosimov, I. Polian, P. Pop, P. Eles, and Z. Peng. Analysis and optimization of fault- tolerant embedded systems with hardened processors. Proc. Design, Automation and Test in Europe, pages 682–687, Nice, F, 2009. (ISBN: 978-1-4244-3781-8) |
[C51] | A. Czutro, I. Polian, M. Lewis, P. Engelke, S. Reddy, and B. Becker. TIGUAN: Thread- parallel Integrated test pattern Generator Utilizing satis?ability ANalysis. In VLSI Design Conf., New-Delhi, pages 227–232, IN, 2009. (ISBN: 978-0-7695-3506-7) |
[C50] | I. Polian, Y. Nakamura, P. Engelke, S. Spinner, K. Miyase, S. Kajihara, B. Becker, and X. Wen. Diagnose realistischer Defekte mit Hilfe des X-Fehlermodells. Proc. GMM/GI/ITG Reliability and Design Conf., pages 155–156, Ingolstadt, D, 2008. (ISBN: 978-3-8007-3119-0; poster) |
[C49] | I. Polian and W. Rao. Selective hardening of NanoPLA circuits. Proc. IEEE Int’l Symp. on Defect and Fault Tolerance, pages 263–271, Cambr /idge, MA, USA, 2008. (ISBN: 978-0-7695- 3365-0) |
[C48] | I. Polian, S.M. Reddy, I. Pomeranz, X. Tang, and B. Becker. On reducing circuit malfunc- tions caused by soft errors. Proc. IEEE Int’l Symp. on Defect and Fault Tolerance, pages 245–253, Cambr /idge, MA, USA, 2008. (ISBN: 978-0-7695-3365-0) |
[C47] | S. Hillebrecht, I. Polian, P. Engelke, B. Becker, M. Keim, and W.-T. Cheng. Extraction, simulation and test generation for interconnect open defects based on enhanced aggressor- victim model. Proc. IEEE Int’l Test Conf., Santa Clara, CA, USA, 2008. (ISBN: 978-1- 4244-2402-3) |
[C46] | D. Nowroth, I. Polian, and B. Becker. A study of cognitive resilience in a JPEG compressor. Proc. IEEE/IFIP Int’l Conf. on Dependable Systems and Networks – Dependable Computing and Communications Symp., pages 32–41, Anchorage, AK, USA, 2008 (ISBN: 978-1-4244- 2398-9). |
[C45] | I. Polian, S. Reddy, and B. Becker. Scalable calculation of logical masking effects for selective hardening against soft errors. Proc. IEEE Int’l Symp. on VLSI, pages 257–262, Montpellier, F, 2008. (ISBN: 978-0-7695-3179-0) |
[C44] | I. Polian, Y. Nakamura, P. Engelke, S. Spinner, K. Miyase, S. Kajihara, B. Becker, and X. Wen. Diagnosis of realistic defects based on the X-Fault model. Formal proc. IEEE Int’l Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 263–266, br /atislava, SK, 2008. (ISBN: 978-1-4244-2276-0; poster) |
[C43] | A. Czutro, N. Houarche, P. Engelke, I. Polian, M. Comte, M. Renovell, and B. Becker. A simulator of small-delay faults caused by resistive-open defects. Proc. IEEE European Test Symp., pages 113–118, Verbania, I, 2008. (ISBN: 978-0-7695-3150-2) |
[C42] | C.G. Zoellin, H.-J. Wunderlich, I. Polian, and B. Becker. Selective hardening in early design steps. Proc. IEEE European Test Symp., pages 185–190, Verbania, I, 2008. (ISBN: 978-0-7695-3150-2) |
[C41] | S. Spinner, I. Polian, P. Engelke, B. Becker, M. Keim, and W.-T. Cheng. Automatic test pattern generation for interconnect open defects. Proc. IEEE VLSI Test Symp., pages 181–186, San Diego, CA, USA, 2008. (ISBN: 978-0-7695-3123-6) |
[C40] | P. Engelke, I. Polian, J. Schloeffel, and B. Becker. Resistive bridging fault simulation of industrial circuits. Proc. Design, Automation and Test in Europe, pages 628–633, Munich, D, 2008. (ISBN: 978-3-9810801-4-8) |
[C39] | P. Engelke, B. Braitling, I. Polian, M. Renovell, and B. Becker. SUPERB: Simulator Utilizing Parallel Evaluation of Resistive bridges. Proc. IEEE Asian Test Symp., pages 433–438, Beijing, CN, 2007. (ISBN: 0-7695-2890-2) |
[C38] | S. Spinner, J. Jiang, I. Polian, P. Engelke, and B. Becker. Simulating open-via defects. Proc. IEEE Asian Test Symp., pages 265–270, Beijing, CN, 2007. (ISBN: 0-7695-2890-2) |
[C37] | I. Polian, D. Nowroth, and B. Becker. Identification of critical errors in imaging applica- tions. Proc. IEEE Int’l On-Line Test Symp., pages 201–202, Heraklion, GR, 2007. (ISBN: 0-7695-2918-6; poster) |
[C36] | J. Hayes, I. Polian, and B. Becker. An analysis framework for transient-error tolerance. Proc. IEEE VLSI Test Symp., pages 249–255, Berkeley, CA, USA, 2007. (ISBN: 0-7695- 2812-0) |
[C35] | B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich. Test und Zu- verlässigkeit nanoelektronischer Systeme. Proc. GMM/GI/ITG Reliability and Design Conf., pages 139–140, Munich, D, 2007. (ISBN: 978-3-8007-3023-0) |
[C34] | I. Polian, J. Hayes, D. Nowroth, and B. Becker. Ein kostenbegrenzter Ansatz zur Reduktion der transienten Fehlerrate. Proc. GMM/GI/ITG Reliability and Design Conf., pages 183– 184, Munich, D, 2007. (ISBN: 978-3-8007-3023-0; poster) |
[C33] | M. Renovell, M. Comte, I. Polian, P. Engelke, and B. Becker. Analyzing the memory effect of resistive open in CMOS random logic. Proc. Int’l Conf. on Design and Test of Integrated Systems in Nanoscale Technology, pages 251–256, Tunis, TN, 2006. (ISBN: 0-7803-9726-6) |
[C32] | I. Polian, B. Becker, M. Nakasato, S. Ohtake, and H. Fujiwara. Low-cost hardening of image processing applications against soft errors. Proc. IEEE Int’l Symp. on Defect and Fault Tolerance, pages 274–279, Arlington, VA, USA, 2006. (ISBN: 0-7695-2706-X) |
[C31] | I. Polian, A. Czutro, S. Kundu, and B. Becker. Power droop testing. Proc. IEEE Int’l Conf. on Computer Design, San Jose, CA, USA, 2006. |
[C30] | P. Engelke, I. Polian, H. Manhaeve, M. Renovell, and B. Becker. Delta-IDDQ testing of resistive short defects. Proc. IEEE Asian Test Symp., pages 63–68, Fukuoka, J, 2006. (ISBN: 0-7695-2628-4) |
[C29] | M. Renovell, M. Comte, I. Polian, P. Engelke, and B. Becker. A specific ATPG technique for resistive open with sequence recursive dependency. Proc. IEEE Asian Test Symp., pages 273–278, Fukuoka, J, 2006. (ISBN: 0-7695-2628-4) |
[C28] | S. Kundu and I. Polian. An improved technique for reducing false alarms due to soft errors. Proc. IEEE Int’l On-Line Test Symp., pages 105–110, Como, I, 2006. (ISBN: 0-7695-2620-9) |
[C27] | J. Eisinger, I. Polian, B. Becker, A. Metzner, S. Thesing, and R. Wilhelm. Automatic iden- tification of timing anomalies for cycle-accurate worst-case execution time analysis. Formal proc. IEEE Int’l Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 15–20, Prague, CZ, 2006. (ISBN: 1-4244-0184-4) |
[C26] | I. Polian and H. Fujiwara. Functional constraints vs. test compression in scan-based delay testing. Proc. Design, Automation and Test in Europe, pages 1039–1044, Munich, D, 2006. (ISBN: 3-9810801-0-6) |
[C25] | I. Polian, J.P. Hayes, T. Fiehn, and B. Becker. A family of logical fault models for reversible circuits. Proc. IEEE Asian Test Symp., pages 422–427, Kolkata, IN, 2005. (ISBN: 0-7695- 2481-8) |
[C24] | S. Kundu, P. Engelke, I. Polian, and B. Becker. On detection of resistive bridging defects by low-temperature and low-voltage testing. Proc. IEEE Asian Test Symp., pages 266–269, Kolkata, IN, 2005. (ISBN: 0-7695-2481-8) |
[C23] | S. Kundu, M.D.T. Lewis, I. Polian, and B. Becker. A soft error emulation system for logic circuits. Proc. Conference on Design of Circuits and Integrated Systems, page 137, Lissabon, P, 2005. (ISBN: 972-99387-2-5) |
[C22] | I. Polian, J.P. Hayes, S. Kundu, and B. Becker. Transient fault characterization in dynamic noisy environments. Proc. IEEE Int’l Test Conf., pages 1039–1048, Austin, TX, USA, 2005. (ISBN: 0-7803-9039-3) |
[C21] | I. Polian, S. Kundu, J.M. Galliere, P. Engelke, M. Renovell, and B. Becker. Resistive bridge fault model evolution from conventional to ultra deep submicron technologies. Proc. IEEE VLSI Test Symp., pages 343–348, Palm Springs, CA, USA, 2005. (ISBN: 0-7695-2314-5) |
[C20] | P. Engelke, V. Gherman, I. Polian, Y. Tang, H.-J. Wunderlich, and B. Becker. Sequence length, area cost and non-target defect coverage tradeoffs in deterministic logic BIST. Formal proc. IEEE Int’l Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 11–18, Sopron, HU, 2005. (ISBN: 963-9364-48-7) |
[C19] | I. Polian, A. Czutro, and B. Becker. Evolutionary optimization in code-based test com- pression. Proc. Design, Automation and Test in Europe, pages 1124–1129, Munich, D, 2005. (ISBN: 0-7695-2288-2) |
[C18] | J.P. Hayes, I. Polian, and B. Becker. Testing for missing-gate faults in reversible circuits. IEEE Asian Test Symp., pages 100–105, Kenting, Taiwan, 2004. (ISBN: 0-7695-2235-1) Selected for the “Best papers compendium 2002-2011” of the IEEE Asian Test Symposium. |
[C17] | Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, and B. Becker. X-masking during logic BIST and its impact on defect coverage. IEEE Int’l Test Conf., pages 442-451, Charlotte, NC, USA, 2004. (ISBN: 0-7803-8581-0) |
[C16] | P. Engelke, I. Polian, M. Renovell, and B. Becker. Automatic test pattern generation for resistive bridging faults. Proc. IEEE European Test Symp., pages 160–165, Ajaccio, Corsica, FR, 2004. (ISBN: 0-7695-2119-3) |
[C15] | P. Engelke, I. Polian, M. Renovell, B. Seshadri, and B. Becker. The pros and cons of very-low-voltage testing: an analysis based on resistive bridging faults. Proc. IEEE VLSI Test Symp., pages 171–178, Napa Valley, CA, USA, 2004. (ISBN: 0-7695-2134-7) |
[C14] | I. Polian and B. Becker. Reducing ATE cost in system-on-chip test. Proc. IFIP VLSI-SoC Conference, pages 337–342, Darmstadt, D, 2003. (ISBN: 3-901882-17-0) |
[C13] | P. Engelke, I. Polian, M. Renovell, and B. Becker. Simulating resistive bridging and stuck- at faults. Proc. IEEE Int’l Test Conf., pages 1051–1059, Charlotte, NC, USA, 2003. (ISBN 0-7803-8107-6) |
[C12] | I. Polian, P. Engelke, M. Renovell, and B. Becker. Modeling feedback bridging faults with non-zero resistance. Formal proc. IEEE European Test Workshop, pages 91–96, Maastricht, NL, 2003. (ISBN: 0-7695-1908-3) |
[C11] | I. Polian and B. Becker. Configuring MISR-based two-pattern BIST using Boolean satisfi- ability. Formal proc. IEEE Int’l Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 73–80, Poznan, PL, 2003. (ISBN: 83-7143-557-6) |
[C10] | I. Polian, W. Günther, and B. Becker. The case for 2-POF. Formal proc. IEEE Int’l Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages 291–292, Poznan, PL, 2003. (poster; ISBN: 83-7143-557-6) |
[C9] | I. Polian, B. Becker, and S. Reddy. Evolutionary optimization of Markov sources for pseudo random scan BIST. Proc. Design, Automation and Test in Europe, pages 1184–1185, Munich, D, 2003. (poster; ISBN: 0-7695-1870-2) |
[C8] | I. Polian, I. Pomeranz, and B. Becker. Exact computation of maximally dominating faults and its application to n-detection tests. Proc. IEEE Asian Test Symp., pages 9–14, Guam, USA, 2002. (ISBN: 0-7695-1825-7) |
[C7] | I. Polian, P. Engelke, and B. Becker. Efficient bridging fault simulation of sequential circuits based on multi-valued logics. Proc. IEEE Int’l Symp. on Multi-Valued Logic, pages 216–222, Boston, MA, USA, 2002. (ISBN: 0-7695-1462-6) |
[C6] | J. Bradford, H. Delong, I. Polian, and B. Becker. Simulating realistic bridging and crosstalk faults in an industrial setting. Formal proc. IEEE European Test Workshop, pages 75–80, Korfu, GR, 2002. (ISBN: 0-7695-1715-3) |
[C5] | I. Polian and B. Becker. Stop & go BIST. Formal proc. IEEE Int’l Online Testing Workshop, pages 147–151, Isle de Bendor, FR, 2002. (ISBN: 0-7695-1641-6) |
[C4] | I. Polian, M. Keim, N. Mallig, and B. Becker. Sequential n-detection criteria: Keep it simple! Formal proc. IEEE Int’l Online Testing Workshop, pages 189–190, Isle de Bendor, FR, 2002. (poster; ISBN: 0-7695-1641-6) |
[C3] | I. Polian, W. Günther, and B. Becker. Efficient pattern-based verification of connections to intellectual property cores. Proc. IEEE Asian Test Symp., pages 443–448, Kyoto, J, 2001. (ISBN: 0-7695-1378-6) |
[C2] | I. Polian and B. Becker. Multiple scan chain design for two-pattern testing. Proc. IEEE VLSI Test Symp., pages 88–93, Marina del Rey, CA, USA, 2001. (ISBN: 0-7695-1122-8) |
[C1] | M. Keim, I. Polian, H. Hengster, and B. Becker. A scalable BIST architecture for delay faults. Formal proc. IEEE European Test Workshop, pages 98–103, Constance, D, 1999. (ISBN: 0-7695-0390-X) |