To the website of the University of Stuttgart

Publication List (September 2018)

Erdös number: 3, H-index: 28 (Harzing’s PoP), 2 best paper awards.

Books, Book Chapters

[B5]

S. Eggersgluess, G. Fey, and I. Polian. Test of Digital Circuits (in German). Oldenbourg,
2014. ISBN: 978-3-486-72013-6.

[B4]

B. Becker, G. Müller, and I. Polian. Digital Tarnkappe: Stealth Technology for the Internet
of Things. In H.-H. Gander, W. Perron, R. Poscher, G. Riescher, T. Württenberger (Hrsg.)
Resilienz in der offenen Gesellschaft. Nomos, Baden-Baden, 2012. ISBN: 978-3-8329-7143-4.

[B3]

B. Becker and I. Polian. Fault modeling for simulation and ATPG. In H.-J. Wunderlich
(editor). Models in Hardware Testing. Frontiers in Electronic Testing. Volume 43. Springer,
New York. 2010. ISBN: 978-90-481-3281-2.

[B2]

I. Polian. On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for
Testability, Industrial Applications. In D. Wagner et al. Ausgezeichnete Informatikdisserta-
tionen 2003 (Best Dissertations in Computer Science 2003). Lecture Notes in Informatics.
Volume D-4. GI. Pages 169-178. 2004. ISBN: 3-88579-408-X.

[B1]

I. Polian. On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design
for Testability, Industrial Applications. VDI Fortschritt-Berichte, Reihe 20, Nr. 377. VDI-
Verlag, Düsseldorf. 218 p. March 2004. ISBN: 3-18-337720-9.

Editorial

[E1]

I. Polian and M. Tehranipoor. Guest Editorial of the Special Session on Hardware Security.
IET Computers & Digital Techniques. 8(6), 2014. (ISSN: 1751-8601)

Journal Articles

[J31]

F. Neugebauer, I. Polian, and J.Hayes. S-box-based random number generation for stochas-
tic computing. Microprocessors and Microsystems (MICPRO). 61, 2018. (ISSN: 0141-9331)

[J30]

F. Neugebauer, I. Polian, and J.Hayes. Framework for quantifying and managing accu-
racy in stochastic circuit design. ACM Jour. Emerging Technologies in Computing Systems
(JETC). 14(2), 2018. (ISSN: 1550-4840)

[J29]

I. Polian. Test and reliability challenges for approximate circuitry. IEEE Embedded Systems
Letters. 10(1), 2018. Pages 26–29. (ISSN:1943-0663)

[J28]

J. Kinseher, M. Voelker, and I. Polian. Improving testability and reliability of advanced
SRAM architectures. IEEE Trans. on Emerging Topics in Computing. Early Access. (ISSN:
2168-6750)

[J27]

A. Paler, I. Polian, K. Nemoto, and S. Devitt. Fault-tolerant high level quantum circuits:
Form, compilation and description. Quantum Science and Technology. 2, 2017. (ISSN:
2058-9565)

[J26]

M. Sauer, B. Becker, and I. Polian. PHAETON: A SAT-based framework for timing-aware
path sensitization. IEEE Trans. on Computers. 65(6), 2016. Pages 1869–1881. (ISSN:
0018-9340)

[J25]

L. Feiten, M. Sauer, T. Schubert, V. Tomashevich, I. Polian, and B. Becker. Formal vulner-
ability analysis of security components IEEE Trans. on Computer-Aided Design of Integrated
Circuits and Systems. 34(8), 2015. Pages 1358–1369. (ISSN: 0278-0070)

[J24]

A. Paler, S. Devitt, K. Nemoto, and I. Polian. Mapping of topological quantum circuits
to physical hardware. Scientific Reports (Nature Publishing Group). 4, 2014. Article No.
4657. (ISSN: 2045-2322)

[J23]

I. Polian. Hardware Security and Test: Friends or Enemies? it-Information Technology.
56(4), 2014. Pages 192–202. (ISSN: 1611-2776)

[J22]

M. Sauer, A. Czutro, T. Schubert, S. Hillebrecht, I. Polian, and B. Becker. SAT-based
analysis of sensitisable paths. IEEE Design & Test of Computers. 30(4), 2013. Pages 81–88.
(ISSN: 2168-2356)

[J21]

F. Hopsch, B. Becker, S. Hellebrand, I. Polian, V. Vermeiren, and H.-J. Wunderlich.
Variation-aware fault modeling. Science China Information Sciences. 54(9), 2011. Pages
1813–1826. (ISSN: 1674-733X)

[J20]

I. Polian and J. Hayes. Selective hardening: toward cost-effective error tolerance. IEEE
Design & Test of Computers. 28(3), 2011. Pages 54–63. (ISSN: 0740-7475)

[J19]

I. Polian, J.P. Hayes, S. Reddy, and B. Becker. Modeling and mitigating transient errors
in logic circuits. IEEE Trans. on Dependable and Secure Computing. 8(4), 2011. Pages
537–547. (ISSN: 1545-5971)

[J18]

I. Polian. Power supply noise: causes, effects, and testing. ASP Jour. Low-Power Elec-
tronics. 6(2), 2010. Pages 326–338. (ISSN: 1546-1998)

[J17]

I. Polian and B. Becker. Fault models and test algorithms for nanoscale technologies. it-
Information Technology. 52(4), 2010. Pages 189–194. (ISSN: 1611-2776)

[J16]

A. Czutro, I. Polian, M. Lewis, P. Engelke, S. Reddy, and B. Becker. TIGUAN: Thread-
parallel Integrated test pattern generator utilizing satisfiability analysis. Int’l Jour. on Par-
allel Programming. 38(3–4), 2010. Pages 185–202. (ISSN: 0885-7458)

[J15]

P. Engelke, B. Becker, M. Renovell, J. Schloeffel, B. Braitling, and I. Polian. SUPERB:
Simulator Utilizing Parallel Evaluation of Resistive Bridges. ACM Trans. on Design Au-
tomation of Electronic Systems. 14(4), 2009. Article No. 56. (ISSN: 1084-4309)

[J14]

P. Engelke, I. Polian, M. Renovell, S. Kundu, B. Seshadri, and B. Becker. On detection
of resistive bridging defects by low-temperature and low-voltage testing. IEEE Trans. on
Computer-Aided Design of Integrated Circuits and Systems. 27(2), 2008. Pages 327–338.
(ISSN: 0278-0070)

[J13]

I. Polian and H. Fujiwara. Functional constraints vs. test compression in scan-based delay
testing Jour. of Electronic Testing: Theory and Applications. 23(5), 2007. Pages 445–455.
(ISSN: 0923-8174)

[J12]

I. Polian, A. Czutro, S. Kundu, and B. Becker. Power droop testing. IEEE Design & Test
Magazine. 24(2), 2007. Pages 276–284 (ISSN: 0740-7475)

[J11]

P. Engelke, I. Polian, M. Renovell, and B. Becker. Simulating resistive bridging and stuck-at
faults. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 25(10),
2006. Pages 2181–2192 (ISSN: 0278-0070)

[J10]

Y. Tang, H.-J. Wunderlich, P. Engelke, I. Polian, B. Becker, J. Schlöffel, F. Hapke, and
M. Wittke. X-masking during logic BIST and its impact on defect coverage. IEEE Trans. on
VLSI Systems, 14(2), 2006. Pages 193–202. (ISSN: 1063-8210)

[J9]

P. Engelke, I. Polian, M. Renovell, and B. Becker. Automatic test pattern generation for
resistive bridging faults. Jour. of Electronic Testing: Theory and Applications, 22(1), 2006.
Pages 61–69. (ISSN: 0923-8174)

[J8]

B. Becker, S. Hellebr /and, I. Polian, B. Straube, and H.-J.Wunderlich. DFG project RealTest
– test and reliability of nano-electronic systems (in German). it-Information Technology.
48(5), 2006. Pages 304–311. (ISSN: 1611-2776)

[J7]

I. Polian, P. Engelke, M. Renovell, and B. Becker. Modeling feedback bridging faults with
non-zero resistance. Jour. of Electronic Testing: Theory and Applications. 21(1), 2005.
Pages 57–69. (ISSN: 0923-8174)

[J6]

I. Polian. Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerech-
ter Entwurf, industrielle Anwendungen. it-Information Technology. 47(3), 2005. Pages
172–174 (ISSN: 1611-2776; abstract of the Ph.D. thesis; selected for publication as one of
the candidates for the German Informatics Society Dissertation Award 2003)

[J5]

I. Polian, I. Pomeranz, S. Reddy and B. Becker. On the use of maximally dominating faults
in n-detection test generation. IEE Proceedings Computers and Digital Techniques, 151(3),
2004. Pages 235–244. (ISSN: 1350-2387)

[J4]

I. Polian and B. Becker. Scalable delay fault BIST for use with low-cost ATE. Jour. of
Electronic Testing: Theory and Applications, 20(2), 2004. Pages 181–197. (ISSN: 0923-
8174)

[J3]

J. Bradford, H. Delong, I. Polian, and B. Becker. Simulating realistic bridging and crosstalk
faults in an industrial setting. Jour. of Electronic Testing: Theory and Applications, 19(4),
2003. Pages 387–395. (ISSN: 0923-8174)

[J2]

I. Polian, W. Günther, and B. Becker. Pattern-based verification of connections to intellectual
property cores. Integration: the VLSI Journal. 35(1), 2003. Pages 25–44. (ISSN: 0167-9260)

[J1]

I. Polian and B. Becker. Multiple scan chain design for two-pattern testing. Jour. of Elec-
tronic Testing: Theory and Applications, 19(1), 2003. Pages 27–48. (ISSN: 0923-8174)

Papers in Formal Proceedings (Refereed)

[C119]

F. Regazzoni, C. Alippi, and I. Polian. Security: The dark side of approximate computing?
Proc. Int’l Conf. on CAD, San Diego, CA, USA, 2018. (Accepted)

[C118]

B. Karp, M. Gay, O. Keren, and I. Polian. Security-oriented code-based architectures for
mitigating fault attacks. Proc. Conf. Design of Circuits and Integrated Systems, Lyon, F,
2018. (Accepted)

[C117]

F. Regazzoni, A. Fowler, and I. Polian. Quantum era challenges for classical computers.
Proc. Int’l Conf. Embedded Computer Systems: Architectures, Modeling and Simulation,
Samos, GR, 2018. (Invited)

[C116]

J. Burchard, M. Gay, A.-S. Messeng Ekossono, J. Horacek, B. Becker, T. Schubert,
M. Kreuzer, and I. Polian. AutoFault: towards automatic construction of algebraic fault
attacks. Proc. Workshop on Fault Diagnosis and Tolerance in Cryptography, Taipeh, TW,
pages 65–72, 2017. (ISBN: 978-1-5386-2948-2)

[C115]

I. Polian, F. Regazzoni, and J. Sepulveda. Introduction to hardware-oriented security
for MPSoCs. Proc. IEEE Int’l System-on-Chip Conf., Munich, D, pages 102–107, 2017.
(Invited; ISBN: 978-1-5386-4034-0)

[C114]

F. Neugebauer, I. Polian, and J. Hayes. Building a better random number generator for
stochastic computing. Proc. Euromicro Conf. on Digital System Design, Vienna, A, 2017.
(ISBN: 978-1-5386-2146-2)

[C113]

J. Burchard, A.-S. Messeng Ekossono, J. Horacek, M. Gay, B. Becker, T. Schubert,
M. Kreuzer, and I. Polian. Towards mixed structural-functional models for algebraic fault
attacks on ciphers. Proc. Int’l Veri?cation and Security Workshop, pages 7–12, Thessaloniki,
GR, 2017. (ISBN: 978-1-5386-1708-3)

[C112]

I. Polian and F. Regazzoni. Counteracting malicious faults in cryptographic circuits.
Proc. IEEE European Test Symp., Limassol, CY, 2017. (Invited, ISBN: 978-1-5090-5457-2)

[C111]

F. Neugebauer, I. Polian, and J. Hayes. Framework for quantifying and managing accu-
racy in stochastic circuit design. Proc. Design, Automation and Test in Europe, Lausanne,
CH, pages 1–6, 2017. (ISBN: 978-3-9815370-8-6)

[C110]

M. Sauer, P. Raiola, L. Feiten, B. Becker, U. Rührmair, and I. Polian. Sensitized Path
PUF: A lightweight embedded physical unclonable function. Proc. Design, Automation and
Test in Europe, Lausanne, CH, pages 680–685, 2017. (ISBN: 978-3-9815370-8-6)

[C109]

J. Kinseher, L. Heiss, and I. Polian. Analyzing the effects of peripheral circuit aging of
embedded SRAM architectures. Proc. Design, Automation and Test in Europe, Lausanne,
CH, pages 852–857, 2017. (ISBN: 978-3-9815370-8-6)

[C108]

F. Regazzoni and I. Polian. Securing the hardware of cyber-physical systems. Proc. Asia
and South Pacific Design Automation Conf., Chiba, J, pages 194–199, 2017. (Invited, ISBN:
978-1-5090-1558-0)

[C107]

M. Sauer, J. Jiang, S. Reimer, K. Miyase, X. Wen, B. Becker, and I. Polian. On optimal
power-aware path sensitization. Proc. IEEE Asian Test Symp., Hiroshima, J, pages 179–184,
2016. (ISBN: 978-1-5090-3808-4)

[C106]

J. Burchard, M. Gay, J. Horacek, A.-S. Messeng Ekossono, T. Schubert, B. Becker, I. Po-
lian, M. Kreuzer. Small scale AES toolbox: Algebraic and propositional formulas, circuit-
implementations and fault equations. Proc. Conf. on Trustworthy Manufacturing and Uti-
lization of Secure Devices, Barcelona, ES, 2016.

[C105]

V. Tomashevich and I. Polian. Memory error resilient detection for massive MIMO sys-
tems. Proc. European Signal Processing Conf., Budapest, H, pages 1623–1627, 2016. (ISBN:
978-0-9928-6265-7)

[C104]

I. Polian. Security aspects of analog and mixed-signal circuits. Proc. IEEE Mixed-Signal
Testing Workshop, Sant Feliu de Guixols, ES, 2016. (Invited, ISBN: 978-1-5090-2751-4)

[C103]

J. Kinseher, M. Voelker, L. Zordan, and I. Polian. Failure mechanisms and test methods
for the SRAM TVC write-assist technique. Proc. IEEE European Test Symp., Amsterdam,
NL, 2016. (ISBN: 978-1-4673-9659-2)

[C102]

V. Tomashevich and I. Polian. Detection performance of MIMO unique word OFDM.
Proc. Int’l ITG Workshop on Smart Antennas, Munich, D, 2016 (ISBN: 978-3-8007-4177-9).

[C101]

J. Kinseher, L. Zordan, I. Polian, and A. Leininger. Improving SRAM test quality by
leveraging self-timed circuits. Proc. Design, Automation and Test in Europe, Dresden, D,
pages 984–989, 2016. (ISBN: 978-3-9815370-6-2)

[C100]

J. Kinseher, L. Zordan, and I. Polian. On the use of assist circuits for improved coupling
fault detection in SRAMs. Proc. IEEE Asian Test Symp., Mumbai, IN, pages 61–66, 2015.
(ISBN: 978-1-4673-9739-1)

[C99]

I. Polian and A. G. Fowler. Design automation challenges for scalable quantum computing.
Proc. ACM/IEEE Design Automation Conf., San Francisco, USA 2015 (Invited, ISBN: 978-
1-4503-3520-1/15/06).

[C98]

J. Kinseher, M. Richter, and I. Polian. On the automated verification of user-defined
MBIST algorithms. Proc. GMM/GI/ITG Reliability and Design Conf., Siegen, D, 2015.
(ISBN: 978-3-8007-4071-0)

[C97]

A. Paler, I. Polian, K. Nemoto, and S. Devitt. A fully fault-tolerant representation of
quantum circuits. Proc. Conf. on Reversible Computation, Grenoble, F, 2015. (LNCS 9138,
ISBN: 978-3-319-20860-2)

[C96]

P. Jovanovic and I. Polian. Fault-based attacks on the Bel-T block cipher family. Proc. De-
sign, Automation and Test in Europe, Grenoble, F, 2015. (ISBN: 978-3-9815-3704-8)

[C95]

R. Kumar, P. Jovanovic, W. Burleson, and I. Polian. Parametric Trojans for fault-injection
attacks on cryptographic hardware. Proc. Fault Diagnosis and Tolerance in Cryptography,
Busan, KR, pages 18–28, 2014. (ISBN: 978-1-4799-6292-1)

[C94]

V. Tomashevich, Y. Neumeier, R. Kumar, O. Keren, and I. Polian. Protecting crypto-
graphic hardware against malicious attacks by nonlinear robust codes. Proc. IEEE Symp.
Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Amsterdam, NL, pages
40-45, 2014. (ISBN: 978-1-4799-6155-9)

[C93]

V. Tomashevich, C. Gimmler, N. Wehn, and I. Polian. Reliability analysis of MIMO
channel preprocessing by fault injection. Proc. IEEE Int’l Conf. on Wireless for Space and
Extreme Environments, Noordwijk, NL, 2014. (ISBN: 978-1-4-4799-5653-1)

[C92]

R. Kumar, P. Jovanovic, and I. Polian. Precise fault injections using voltage and temper-
ature manipulation for differential cryptanalysis Proc. IEEE On-Line Test Symp., Platja
d’Aro, E, pages 43–38, 2014. (ISBN: 978-1-4799-5323-3)

[C91]

A. Paler, S. Devitt, K. Nemoto, and I. Polian. Cross-level validation of topological quantum
circuits. Proc. Conf. on Reversible Computation, Kyoto, J, pages 189–200, 2014. (LNCS
8507, ISBN 978-3-319-08494-7)

[C90]

I. Polian, J. Jiang, and A. Singh. Detection conditions for errors in self-adaptive better-
than-worst-case designs. Proc. IEEE European Test Symp., Paderborn, D, 2014. (ISBN:
978-1-4799-3415-7)

[C89]

M. Sauer, I. Polian, M. Imhof, A. Mumtaz, E. Schneider, A. Czutro, H.-J. Wunderlich,
and B. Becker. Variation-aware deterministic ATPG. Proc. IEEE European Test Symp.,
Paderborn, D, 2014. (ISBN: 978-1-4799-3415-7) Best Paper Award

[C88]

V. Tomashevich, C. Gimmler, C. Fesl, N. Wehn, and I. Polian. A new architecture for
minimum mean square error sorted QR decomposition for MIMO wireless communication
systems. Proc. IEEE Symp. on Design and Diagnostics of Electronic Circuits and Systems,
Warsaw, PL, pages 246–249, 2014. (Poster, ISBN: 978-1-4799-4560-3)

[C87]

A. Paler, S. Devitt, K. Nemoto, and I. Polian. Software-based Pauli tracking in fault-
tolerant quantum circuits. Proc. Design, Automation and Test in Europe, Dresden, D, 2014.
(ISBN: 978-3-9815370-2-4, Interactive Presentation)

[C86]

R. K. Uppu, R. T. Uppu, A. Singh, and I. Polian. Better-than-worst-case timing design
with latch buffers on short paths. Proc. VLSI Design Conf., Mumbai, IN, pages 133–138,
2014. (ISSN: 1063-9667)

[C85]

A. Czutro, I. Polian, S. M. Reddy, and B. Becker. SAT-based test pattern generation with
improved dynamic compaction. Proc. VLSI Design Conf., pages 56–61, Mumbai, IN, 2014.
(ISSN: 1063-9667)

[C84]

J. Jiang, M. Comte, M. Aparicio Rodriguez, F. Azais, M. Renovell, and I. Polian. MIRID:
Mixed-mode IR-drop Induced Delay simulator. Proc. IEEE Asian Test Symp., Yilan, Tai-
wan, pages 177–182, 2013. (ISBN: 1081-7735)

[C83]

A. Paler, I. Polian, J. Kinseher, and J.P. Hayes. Approximate simulation of circuits with
probabilistic behavior. Proc. IEEE Symp. Defect and Fault Tolerance in VLSI and Nan-
otechnology Systems, New York, USA, pages 95–100, 2013. (ISBN: 978-1-4799-1583-5)

[C82]

M. Sauer, S. Reimer, T. Schubert, I. Polian, and B. Becker. Efficient SAT-based dynamic
compaction and relaxation for longest sensitizable paths. Proc. Design, Automation and
Test in Europe, Grenoble, F, pages 448–453, 2013 (ISBN: 978-1-4673-5071-6).

[C81]

M. Sauer, S. Reimer, I. Polian, T. Schubert, and B. Becker. Provably optimal test cube
generation using Quantified Boolean Formula solving. Proc. Asia and South Pacific Design
Automation Conf., Yokohama, J, pages 533–539, 2013. (ISBN: 978-1-4673-3029-9) Nomi-
nated for Best Paper Award

[C80]

A. Czutro, M.E. Imhof, J. Jiang, A. Mumtaz, M. Sauer, B. Becker, I. Polian, and H.-J.
Wunderlich.Variation-aware fault grading Proc. IEEE Asian Test Symp., Niigata, J, pages
344–349, 2012. (ISBN: 978-0-7695-4876-0)

[C79]

M. Sauer, A. Czutro, I. Polian, and B. Becker. Small-delay-fault ATPG with waveform
accuracy. Proc. IEEE/ACM Int’l Conf. on CAD, San Jose, CA, USA, pages 30–36, 2012.
(ISBN: 978-1-4577-1398-9)

[C78]

A. Paler, S. Devitt, K. Nemoto, and I. Polian. Synthesis of topological quantum circuits.
Proc. IEEE/ACM Int’l Symp. on Nanoscale Architectures, Amsterdam, NL, pages 181–187,
2012. (ISBN: 978-1-4503-1671-2)

[C77]

M. Aparicio Rodriguez, M. Comte, F. Azais, Y. Bertrand, M. Renovell, J. Jiang, I. Polian,
and B. Becker. An IR-drop simulation principle oriented to delay testing. Proc. Design of
Circuits and Integrated Systems Conf., Avignon, F, 2012.

[C76]

L. Feiten, M. Sauer, T. Schubert, A. Czutro, E. Boehl, I. Polian, and B. Becker. #SAT-
based vulnerability analysis of security components – A case study.
Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Austin, TX, USA, pages 49–54, 2012. (ISBN: 978-1-4673-3043-5)

[C75]

M. Sauer, S. Kupferschmidt, A. Czutro, I. Polian, S. Reddy, and B. Becker. Functional test
of small-delay faults using SAT and Craig interpolation. Proc. Int’l Test Conf., Anaheim,
CA, USA, paper 6.3, 2012. (ISBN: 978-1-4673-1595-1)

[C74]

V. Tomashevich, S. Srinivasan, F. Foerg, and I. Polian. Cross-level protection of circuits
against faults and malicious attacks Proc. IEEE Int’l On-Line Test Symp., Sitges, E, pages
150–155, 2012. (ISBN: 978-1-4673-2082-5)

[C73]

P. Jovanovic, M. Kreuzer, and I. Polian. A fault attack on the LED block cipher. Proc. Int’l
Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE), Darm-
stadt, D, pages 120–134, 2012. (LNCS 7275, ISBN: 978-3-642-29911-7)

[C72]

M. Sauer, A. Czutro, B. Becker, and I. Polian. On the quality of test vectors for post-silicon
characterization. Proc. IEEE European Test Symp., Annecy, F, 2012. (ISBN: 978-1-4673-
0696-6)

[C71]

A. Czutro, M. Sauer, I. Polian, and B. Becker. Multi-conditional SAT-ATPG for power-
droop testing. Proc. IEEE European Test Symp., Annecy, F, 2012. (ISBN: 978-1-4673-0696-6)

[C70]

A. Czutro, M. Sauer, T. Schubert, I. Polian, and B. Becker. SAT-ATPG using preferences
for improved detection of complex defect mechanisms. Proc. IEEE VLSI Test Symp., Maui,
HI, USA, pages 170–175, 2012. (ISBN: 978-1-4673-1073-4)

[C69]

J. Jiang, M. Sauer, A. Czutro, B. Becker, and I. Polian. On the optimality of K longest
path generation algorithm under memory limitations. Proc. Design, Automation and Test
in Europe, Dresden, D, pages 418–423, 2012. (ISBN: 978-3-9810801-8-6)

[C68]

A. Paler, I. Polian, and J.P. Hayes. Detection and diagnosis of faulty quantum circuits.
Proc. Asia and South Pacific Design Automation Conf., Sydney, AUS, pages 181–186, 2012.
(ISBN: 978-1-4673-0772-7)

[C67]

M. Sauer, J. Jiang A. Czutro, I. Polian, and B. Becker. Efficient SAT-based search for
longest sensitisable paths. Proc. IEEE Asian Test Symp., New Delhi, IN, pages 108–113,
2011. (ISBN: 978-1-4577-1984-4)

[C66]

M. Sauer, V. Tomashevich, J. Müller, M. Lewis, A. Spilla, I. Polian, B. Becker, and W. Bur-
gard. An FPGA-based framework for run-time injection and analysis of soft errors in mi-
croprocessors. Proc. IEEE Int’l On-Line Test Symp., Athens, GR, pages 182–185, 2011.
(ISBN: 978-1-4577-1053-7)

[C65]

M. Sauer, A. Czutro, I. Polian, and B. Becker. Estimation of component criticality in
early design steps. Proc. IEEE Int’l On-Line Test Symp., Athens, GR, pages 104–110, 2011.
(ISBN: 978-1-4577-1053-7)

[C64]

A. Paler, A. Alaghi, I. Polian, and J.P. Hayes. Tomographic testing and validation of
probabilistic circuits. Proc. IEEE European Test Symp., Trondheim, NO, pages 63–68,
2011. (ISBN: 978-1-4577-0483-3)

[C63]

I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, and P. Maxwell. Towards variation-
aware test methods. Proc. IEEE European Test Symp., Trondheim, NO, 2011, pages 219–
225. (ISBN: 978-1-4577-0483-3)

[C62]

M. Sauer, A. Czutro, T. Schubert, S. Hillebrecht, I. Polian, and B. Becker. SAT-based anal-
ysis of sensitisable paths. Proc. IEEE Int’l Symp. on Design and Diagnostics of Electronic
Circuits and Systems (DDECS), Cottbus, pages 93–98, 2011. (ISBN: 978-1-4244-9755-3).
Best Paper Award (Test track)

[C61]

P. Krause and I. Polian. Adaptive voltage over-scaling for resilient applications. Proc. De-
sign, Automation and Test in Europe, Grenoble, F, 2011. (ISBN: 978-1-61284-208-0)

[C60]

F. Hopsch, B. Becker, S. Hellebrand, I. Polian, V. Vermeiren, and H.-J. Wunderlich.
Variation-aware fault modeling. Proc. IEEE Asian Test Symp., pages 87–93, Shanghai,
China, 2010. (ISBN: 978-0-7695-4248-5) Selected for the “Best papers compendium
2002-2011” of the IEEE Asian Test Symposium.

[C59]

I. Polian and J.P. Hayes. Modeling faults in reversible circuits. Proc. IEEE East-West
Design and Test Symp., pages 376–381, St. Petersburg, Russia, 2010. (Invited)

[C58]

B. Becker, S. Hellebrand, I. Polian, B. Straube, V. Vermeiren, and H.-J. Wunderlich.
Massive statistical process variations: A grand challenge for testing nanoelectronic circuits.
Proc. Workshop on Dependable and Secure Nanocomputing, pages 95–100, Chicago, IL, USA,
2010. (ISBN: 978-1-4244-7729-6)

[C57]

A. Czutro, I. Polian, P. Engelke, S. Reddy, and B. Becker. Dynamic compaction in SAT-
based ATPG. Proc. IEEE Asian Test Symp., pages 187–190, Taichung, Taiwan, 2009. (ISBN:
978-0-7695-3864-8)

[C56]

V. Izosimov, I. Polian, P. Pop, P. Eles, and Z. Peng. Analyse und Optimierung von
fehlertoleranten eingebetteten Systemen mit gehärteten Prozessoren. Proc. GMM/GI/ITG
Reliability and Design Conf., pages 79–80, Stuttgart, D, 2009. (ISBN: 978-3-8007-3178-7;
poster)

[C55]

M. Hunger, S. Hellebr /and, A. Czutro, I. Polian, and B. Becker. ATPG-based grading of
strong fault-secureness. Proc. IEEE Int’l On-Line Test Symp., pages 269–274, Lisbon, PT,
2009. (ISBN: 978-1-4244-4596-7)

[C54]

N. Houarche, M. Comte, M. Renovell, A. Czutro, P. Engelke, I. Polian, and B. Becker. An
electrical model for the fault simulation of small delay faults caused by crosstalk-aggravated
resistive short defects. Proc. IEEE VLSI Test Symp., pages 21–26, Santa Cruz, CA, USA,
2009. (ISBN: 978-0-7695-3598-2)

[C53]

K.P. Ganeshpure, I. Polian, S. Kundu, and B. Becker. Reducing temperature variability
by routing heat pipes. Proc. ACM Great Lakes Symp. on VLSI , Boston, MA, USA, pages
63–68, 2009. (ISBN: 978-1-60558-522-2).

[C52]

V. Izosimov, I. Polian, P. Pop, P. Eles, and Z. Peng. Analysis and optimization of fault-
tolerant embedded systems with hardened processors. Proc. Design, Automation and Test
in Europe, pages 682–687, Nice, F, 2009. (ISBN: 978-1-4244-3781-8)

[C51]

A. Czutro, I. Polian, M. Lewis, P. Engelke, S. Reddy, and B. Becker. TIGUAN: Thread-
parallel Integrated test pattern Generator Utilizing satis?ability ANalysis. In VLSI Design
Conf., New-Delhi, pages 227–232, IN, 2009. (ISBN: 978-0-7695-3506-7)

[C50]

I. Polian, Y. Nakamura, P. Engelke, S. Spinner, K. Miyase, S. Kajihara, B. Becker, and
X. Wen. Diagnose realistischer Defekte mit Hilfe des X-Fehlermodells. Proc. GMM/GI/ITG
Reliability and Design Conf., pages 155–156, Ingolstadt, D, 2008. (ISBN: 978-3-8007-3119-0;
poster)

[C49]

I. Polian and W. Rao. Selective hardening of NanoPLA circuits. Proc. IEEE Int’l Symp. on
Defect and Fault Tolerance, pages 263–271, Cambr /idge, MA, USA, 2008. (ISBN: 978-0-7695-
3365-0)

[C48]

I. Polian, S.M. Reddy, I. Pomeranz, X. Tang, and B. Becker. On reducing circuit malfunc-
tions caused by soft errors. Proc. IEEE Int’l Symp. on Defect and Fault Tolerance, pages
245–253, Cambr /idge, MA, USA, 2008. (ISBN: 978-0-7695-3365-0)

[C47]

S. Hillebrecht, I. Polian, P. Engelke, B. Becker, M. Keim, and W.-T. Cheng. Extraction,
simulation and test generation for interconnect open defects based on enhanced aggressor-
victim model. Proc. IEEE Int’l Test Conf., Santa Clara, CA, USA, 2008. (ISBN: 978-1-
4244-2402-3)

[C46]

D. Nowroth, I. Polian, and B. Becker. A study of cognitive resilience in a JPEG compressor.
Proc. IEEE/IFIP Int’l Conf. on Dependable Systems and Networks – Dependable Computing
and Communications Symp., pages 32–41, Anchorage, AK, USA, 2008 (ISBN: 978-1-4244-
2398-9).

[C45]

I. Polian, S. Reddy, and B. Becker. Scalable calculation of logical masking effects for
selective hardening against soft errors. Proc. IEEE Int’l Symp. on VLSI, pages 257–262,
Montpellier, F, 2008. (ISBN: 978-0-7695-3179-0)

[C44]

I. Polian, Y. Nakamura, P. Engelke, S. Spinner, K. Miyase, S. Kajihara, B. Becker, and
X. Wen. Diagnosis of realistic defects based on the X-Fault model. Formal proc. IEEE Int’l
Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages
263–266, br /atislava, SK, 2008. (ISBN: 978-1-4244-2276-0; poster)

[C43]

A. Czutro, N. Houarche, P. Engelke, I. Polian, M. Comte, M. Renovell, and B. Becker. A
simulator of small-delay faults caused by resistive-open defects. Proc. IEEE European Test
Symp., pages 113–118, Verbania, I, 2008. (ISBN: 978-0-7695-3150-2)

[C42]

C.G. Zoellin, H.-J. Wunderlich, I. Polian, and B. Becker. Selective hardening in early
design steps. Proc. IEEE European Test Symp., pages 185–190, Verbania, I, 2008. (ISBN:
978-0-7695-3150-2)

[C41]

S. Spinner, I. Polian, P. Engelke, B. Becker, M. Keim, and W.-T. Cheng. Automatic
test pattern generation for interconnect open defects. Proc. IEEE VLSI Test Symp., pages
181–186, San Diego, CA, USA, 2008. (ISBN: 978-0-7695-3123-6)

[C40]

P. Engelke, I. Polian, J. Schloeffel, and B. Becker. Resistive bridging fault simulation of
industrial circuits. Proc. Design, Automation and Test in Europe, pages 628–633, Munich,
D, 2008. (ISBN: 978-3-9810801-4-8)

[C39]

P. Engelke, B. Braitling, I. Polian, M. Renovell, and B. Becker. SUPERB: Simulator
Utilizing Parallel Evaluation of Resistive bridges. Proc. IEEE Asian Test Symp., pages
433–438, Beijing, CN, 2007. (ISBN: 0-7695-2890-2)

[C38]

S. Spinner, J. Jiang, I. Polian, P. Engelke, and B. Becker. Simulating open-via defects.
Proc. IEEE Asian Test Symp., pages 265–270, Beijing, CN, 2007. (ISBN: 0-7695-2890-2)

[C37]

I. Polian, D. Nowroth, and B. Becker. Identification of critical errors in imaging applica-
tions. Proc. IEEE Int’l On-Line Test Symp., pages 201–202, Heraklion, GR, 2007. (ISBN:
0-7695-2918-6; poster)

[C36]

J. Hayes, I. Polian, and B. Becker. An analysis framework for transient-error tolerance.
Proc. IEEE VLSI Test Symp., pages 249–255, Berkeley, CA, USA, 2007. (ISBN: 0-7695-
2812-0)

[C35]

B. Becker, I. Polian, S. Hellebrand, B. Straube, and H.-J. Wunderlich. Test und Zu-
verlässigkeit nanoelektronischer Systeme. Proc. GMM/GI/ITG Reliability and Design Conf.,
pages 139–140, Munich, D, 2007. (ISBN: 978-3-8007-3023-0)

[C34]

I. Polian, J. Hayes, D. Nowroth, and B. Becker. Ein kostenbegrenzter Ansatz zur Reduktion
der transienten Fehlerrate. Proc. GMM/GI/ITG Reliability and Design Conf., pages 183–
184, Munich, D, 2007. (ISBN: 978-3-8007-3023-0; poster)

[C33]

M. Renovell, M. Comte, I. Polian, P. Engelke, and B. Becker. Analyzing the memory effect
of resistive open in CMOS random logic. Proc. Int’l Conf. on Design and Test of Integrated
Systems in Nanoscale Technology, pages 251–256, Tunis, TN, 2006. (ISBN: 0-7803-9726-6)

[C32]

I. Polian, B. Becker, M. Nakasato, S. Ohtake, and H. Fujiwara. Low-cost hardening of
image processing applications against soft errors. Proc. IEEE Int’l Symp. on Defect and
Fault Tolerance, pages 274–279, Arlington, VA, USA, 2006. (ISBN: 0-7695-2706-X)

[C31]

I. Polian, A. Czutro, S. Kundu, and B. Becker. Power droop testing. Proc. IEEE Int’l
Conf. on Computer Design, San Jose, CA, USA, 2006.

[C30]

P. Engelke, I. Polian, H. Manhaeve, M. Renovell, and B. Becker. Delta-IDDQ testing of
resistive short defects. Proc. IEEE Asian Test Symp., pages 63–68, Fukuoka, J, 2006. (ISBN:
0-7695-2628-4)

[C29]

M. Renovell, M. Comte, I. Polian, P. Engelke, and B. Becker. A specific ATPG technique
for resistive open with sequence recursive dependency. Proc. IEEE Asian Test Symp., pages
273–278, Fukuoka, J, 2006. (ISBN: 0-7695-2628-4)

[C28]

S. Kundu and I. Polian. An improved technique for reducing false alarms due to soft errors.
Proc. IEEE Int’l On-Line Test Symp., pages 105–110, Como, I, 2006. (ISBN: 0-7695-2620-9)

[C27]

J. Eisinger, I. Polian, B. Becker, A. Metzner, S. Thesing, and R. Wilhelm. Automatic iden-
tification of timing anomalies for cycle-accurate worst-case execution time analysis. Formal
proc. IEEE Int’l Workshop on Design and Diagnostics of Electronic Circuits and Systems
(DDECS), pages 15–20, Prague, CZ, 2006. (ISBN: 1-4244-0184-4)

[C26]

I. Polian and H. Fujiwara. Functional constraints vs. test compression in scan-based delay
testing. Proc. Design, Automation and Test in Europe, pages 1039–1044, Munich, D, 2006.
(ISBN: 3-9810801-0-6)

[C25]

I. Polian, J.P. Hayes, T. Fiehn, and B. Becker. A family of logical fault models for reversible
circuits. Proc. IEEE Asian Test Symp., pages 422–427, Kolkata, IN, 2005. (ISBN: 0-7695-
2481-8)

[C24]

S. Kundu, P. Engelke, I. Polian, and B. Becker. On detection of resistive bridging defects
by low-temperature and low-voltage testing. Proc. IEEE Asian Test Symp., pages 266–269,
Kolkata, IN, 2005. (ISBN: 0-7695-2481-8)

[C23]

S. Kundu, M.D.T. Lewis, I. Polian, and B. Becker. A soft error emulation system for logic
circuits. Proc. Conference on Design of Circuits and Integrated Systems, page 137, Lissabon,
P, 2005. (ISBN: 972-99387-2-5)

[C22]

I. Polian, J.P. Hayes, S. Kundu, and B. Becker. Transient fault characterization in dynamic
noisy environments. Proc. IEEE Int’l Test Conf., pages 1039–1048, Austin, TX, USA, 2005.
(ISBN: 0-7803-9039-3)

[C21]

I. Polian, S. Kundu, J.M. Galliere, P. Engelke, M. Renovell, and B. Becker. Resistive bridge
fault model evolution from conventional to ultra deep submicron technologies. Proc. IEEE
VLSI Test Symp., pages 343–348, Palm Springs, CA, USA, 2005. (ISBN: 0-7695-2314-5)

[C20]

P. Engelke, V. Gherman, I. Polian, Y. Tang, H.-J. Wunderlich, and B. Becker. Sequence
length, area cost and non-target defect coverage tradeoffs in deterministic logic BIST. Formal
proc. IEEE Int’l Workshop on Design and Diagnostics of Electronic Circuits and Systems
(DDECS), pages 11–18, Sopron, HU, 2005. (ISBN: 963-9364-48-7)

[C19]

I. Polian, A. Czutro, and B. Becker. Evolutionary optimization in code-based test com-
pression. Proc. Design, Automation and Test in Europe, pages 1124–1129, Munich, D, 2005.
(ISBN: 0-7695-2288-2)

[C18]

J.P. Hayes, I. Polian, and B. Becker. Testing for missing-gate faults in reversible circuits.
IEEE Asian Test Symp., pages 100–105, Kenting, Taiwan, 2004. (ISBN: 0-7695-2235-1)
Selected for the “Best papers compendium 2002-2011” of the IEEE Asian Test
Symposium.

[C17]

Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, and
B. Becker. X-masking during logic BIST and its impact on defect coverage. IEEE Int’l Test
Conf., pages 442-451, Charlotte, NC, USA, 2004. (ISBN: 0-7803-8581-0)

[C16]

P. Engelke, I. Polian, M. Renovell, and B. Becker. Automatic test pattern generation for
resistive bridging faults. Proc. IEEE European Test Symp., pages 160–165, Ajaccio, Corsica,
FR, 2004. (ISBN: 0-7695-2119-3)

[C15]

P. Engelke, I. Polian, M. Renovell, B. Seshadri, and B. Becker. The pros and cons of
very-low-voltage testing: an analysis based on resistive bridging faults. Proc. IEEE VLSI
Test Symp., pages 171–178, Napa Valley, CA, USA, 2004. (ISBN: 0-7695-2134-7)

[C14]

I. Polian and B. Becker. Reducing ATE cost in system-on-chip test. Proc. IFIP VLSI-SoC
Conference, pages 337–342, Darmstadt, D, 2003. (ISBN: 3-901882-17-0)

[C13]

P. Engelke, I. Polian, M. Renovell, and B. Becker. Simulating resistive bridging and stuck-
at faults. Proc. IEEE Int’l Test Conf., pages 1051–1059, Charlotte, NC, USA, 2003. (ISBN
0-7803-8107-6)

[C12]

I. Polian, P. Engelke, M. Renovell, and B. Becker. Modeling feedback bridging faults with
non-zero resistance. Formal proc. IEEE European Test Workshop, pages 91–96, Maastricht,
NL, 2003. (ISBN: 0-7695-1908-3)

[C11]

I. Polian and B. Becker. Configuring MISR-based two-pattern BIST using Boolean satisfi-
ability. Formal proc. IEEE Int’l Workshop on Design and Diagnostics of Electronic Circuits
and Systems (DDECS), pages 73–80, Poznan, PL, 2003. (ISBN: 83-7143-557-6)

[C10]

I. Polian, W. Günther, and B. Becker. The case for 2-POF. Formal proc. IEEE Int’l
Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pages
291–292, Poznan, PL, 2003. (poster; ISBN: 83-7143-557-6)

[C9]

I. Polian, B. Becker, and S. Reddy. Evolutionary optimization of Markov sources for pseudo
random scan BIST. Proc. Design, Automation and Test in Europe, pages 1184–1185, Munich,
D, 2003. (poster; ISBN: 0-7695-1870-2)

[C8]

I. Polian, I. Pomeranz, and B. Becker. Exact computation of maximally dominating faults
and its application to n-detection tests. Proc. IEEE Asian Test Symp., pages 9–14, Guam,
USA, 2002. (ISBN: 0-7695-1825-7)

[C7]

I. Polian, P. Engelke, and B. Becker. Efficient bridging fault simulation of sequential circuits
based on multi-valued logics. Proc. IEEE Int’l Symp. on Multi-Valued Logic, pages 216–222,
Boston, MA, USA, 2002. (ISBN: 0-7695-1462-6)

[C6]

J. Bradford, H. Delong, I. Polian, and B. Becker. Simulating realistic bridging and crosstalk
faults in an industrial setting. Formal proc. IEEE European Test Workshop, pages 75–80,
Korfu, GR, 2002. (ISBN: 0-7695-1715-3)

[C5]

I. Polian and B. Becker. Stop & go BIST. Formal proc. IEEE Int’l Online Testing Workshop,
pages 147–151, Isle de Bendor, FR, 2002. (ISBN: 0-7695-1641-6)

[C4]

I. Polian, M. Keim, N. Mallig, and B. Becker. Sequential n-detection criteria: Keep it simple!
Formal proc. IEEE Int’l Online Testing Workshop, pages 189–190, Isle de Bendor, FR, 2002.
(poster; ISBN: 0-7695-1641-6)

[C3]

I. Polian, W. Günther, and B. Becker. Efficient pattern-based verification of connections to
intellectual property cores. Proc. IEEE Asian Test Symp., pages 443–448, Kyoto, J, 2001.
(ISBN: 0-7695-1378-6)

[C2]

I. Polian and B. Becker. Multiple scan chain design for two-pattern testing. Proc. IEEE
VLSI Test Symp., pages 88–93, Marina del Rey, CA, USA, 2001. (ISBN: 0-7695-1122-8)

[C1]

M. Keim, I. Polian, H. Hengster, and B. Becker. A scalable BIST architecture for delay
faults. Formal proc. IEEE European Test Workshop, pages 98–103, Constance, D, 1999.
(ISBN: 0-7695-0390-X)

Interdisciplinary Papers in Non Computer Science Conferences (refereed with varying degree of thoroughness)

[I6]

A. Paler, S. Devitt, K. Nemoto, and I. Polian. Classical compilers for gate optimisation in
fault-tolerant quantum computing. Int’l Conf. on Quantum Communication, Measurement
and Computing, Vienna, A, 2012. (poster P1-54)

[I5]

P. Jovanovic, M. Kreuzer, and I. Polian. An algebraic fault attack on the LED block cipher.
Proc. Int’l Conf. on Symbolic Computation and Cryptography, Castro Urdiales, E, 2012.

[I4]

S. Hillebrecht, I. Polian, P. Ruther, S. Herwik, B. Becker, and O. Paul. Reliability charac-
terization of interconnects in CMOS integrated circuits under mechanical stress. Proc. Int’l
Reliability Physics Symp., pages 562–567, Montreal, CDN, 2009. (ISBN: 978-1-4244-2888-5)

[I3]

S. Spinner, M. Doelle, P. Ruther, I. Polian, O. Paul, and B. Becker. A system for electro-
mechanical reliability testing of MEMS devices. Proc. ASM International Symp. for Testing
and Failure Analysis, pages 147–152, Austin, TX, USA, 2006. (ISBN: 0-87170-844-2)

[I2]

S. Spinner, I. Polian, B. Becker, P. Ruther, and O. Paul. A system for the calibration
and reliability testing of MEMS devices under mechanical stress. Proc. VDE Microsystem
Technology Congress, pages 861–864, Munich, D, 2007. (ISBN: 978-3-8007-3061-2; poster)

[I1]

S. Spinner, J. Bartolomeyczik, B. Becker, M. Doelle, O. Paul, I. Polian P. Roth, K. Seitz, and
P. Ruther. Electromechanical reliability testing of three-axial force sensors. Proc. Design,
Test, Integration and Packaging of MEMS/MOEMS, pages 77–82, Stresa, I, 2006. (ISBN:
2-916187-03-0)

Workshop Contributions (Refereed)

[W56]

B. Karp, M. Gay, O. Keren, and I. Polian. Detection and correction of malicious and
natural faults in cryptographic modules. In Int’l Workshop on Security Proofs for Embedded
Systems (PROOFS, co-located with CHES’17), Amsterdam, NL, 2018 (Accepted).

[W55]

F. Neugebauer, I. Polian, and J.Hayes. On the maximum function in stochastic neural
networks. In Workshop on Approximate Computing, Bremen, DE, 2018.

[W54]

J. Burchard, A.-S. Messeng Ekossono, J. Horacek, M. Gay, B. Becker, T. Schubert,
M. Kreuzer, and I. Polian. Towards mixed structural-functional models for algebraic fault
attacks on ciphers. In Workshop on Reliability, Security and Quality (RESCUE, co-located
with ETS’17), Limassol, CY, 2017.

[W53]

J. Kinseher, L. Heiss, and I. Polian. Analyzing the e?ects of peripheral circuit aging
of embedded SRAM architectures. In GI/GMM/ITG Workshop “Testmethoden und Zu-
verlässigkeit von Schaltungen und Systemen”, Lübeck, D, 2017.

[W52]

M. Sauer, J. Jiang, S. Reimer, K. Miyase, X. Wen, B. Becker, and I. Polian. On opti-
mal power-aware path sensitization. In GI/GMM/ITG Workshop “Testmethoden und Zu-
verlässigkeit von Schaltungen und Systemen”, Lübeck, D, 2017.

[W51]

I. Polian. Hardware Trojans in early design steps: An emerging threat. In IEEE Int’l
Veri?cation and Security Workshop, Sant Feliu de Guixols, ES, 2016.

[W50]

M. Sauer, L. Feiten, B. Becker, U. Ruehrmair, and I. Polian. Towards turning arbitrary
circuits into physical unclonable functions. In TRUDEVICE Workshop (co-located with
DATE), Dresden, D, 2016.

[W49]

L. Batina, B. Becker, G. Di Natale, M.-L. Flottes, S. Hamdioui, N. Mentens, I. Polian, and
B. Rouzeyre. Manufacturing testing and fault-tolerance of secure devices. In GI/GMM/ITG
Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Siegen, D,
2016.

[W48]

J. Kinseher, L. B. Zordan, I. Polian, and A. Leininger. Improving SRAM test qual-
ity by leveraging self-timed circuits. In GI/GMM/ITG Workshop “Testmethoden und Zu-
verlässigkeit von Schaltungen und Systemen”, Siegen, D, 2016.

[W47]

I. Polian. Test and reliability challenges for approximate circuitry. In Workshop on Ap-
proximate Computing, Paderborn, D, 2015.

[W46]

M. Cortez, S. Hamdioui, G. Di Natale, M.-L. Flottes, B. Rouzeyre, and I. Polian. Multi-
segment enhanced scan-chains for secure ICs. In TRUDEVICE Workshop (co-located with
CHES), San Malo, FR, 2015.

[W45]

V. Tomashevich, C. Gimmler, N. Wehn, and I. Polian. Reliability analysis of MIMO
channel preprocessing by fault injection. In Joint MEDIAN – TRUDEVICE Open Forum,
Amsterdam, NL, 2014.

[W44]

R. Kumar, P. Jovanovic, W. P. Burleson, and I. Polian. Parametric Trojans for Fault-
based Attacks on Cryptographic Hardware. In Design Automation Conf., San Francisco,
CA, USA, 2014. (work-in-progress track).

[W43]

W. Wallner, A. Paler, and I. Polian. QuantumEDA – A Visualization and Design Envi-
ronment for topological Quantum Circuits. In Design Automation and Test in Europe Conf.
University Booth, Dresden, D, 2014.

[W42]

R. Kumar, P. Jovanovic, W. P. Burleson, and I. Polian. Improved manufacturing pro-
cess level techniques for Trojan hardware insertion with low detection probability.
In GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Syste-
men”, Kloster Banz, D, 2014.

[W41]

I. Polian, J. Jiang, and A. Singh. Detection conditions for errors in self-adaptive better-
than-worst-case designs. In GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen”, Kloster Banz, D, 2014.

[W40]

P. Jovanovic, M. Kreuzer, and I. Polian. Multi-stage fault attacks on block ciphers.
In IEEE Workshop on RTL ATPG and DfT, Jiaosi, TW, 2013.

[W39]

A. Paler, S. Devitt, K. Nemoto, and I. Polian. Visualization and debug of topological
quantum computers. In IEEE European Test Symp. (workshop-style paper track), Avignon,
F, 2013.

[W38]

M. Comte, M. Aparicio, F. Azais, M. Renovell, J. Jiang, I. Polian, and B. Becker. Pre-
characterization procedure for a mixed mode simulation of IR-drop induced delays. In IEEE
Latin American Test Workshop, Cordoba, ARG, 2013.

[W37]

I. Polian.TRUDEVICE: a COST Action in Europe. Invited talk. In IEEE Workshop
on RTL ATPG and DfT, Niigata, J, 2012.

[W36]

M. Sauer, S. Kupferschmid, A. Czutro, I. Polian, S. Reddy, and B. Becker. Functional
justi?cation in sequential circuits using SAT and Craig interpolation. In GI/GMM/ITG
Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Cottbus, D,
2012.

[W35]

A. Czutro, M. Sauer, I. Polian, and B. Becker. Multi-conditional ATPG using SAT with
preferences. In GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltun-
gen und Systemen”, Cottbus, D, 2012.

[W34]

J. Jiang, M. Sauer, A. Czutro, B. Becker, and I. Polian. On the optimality of K longest
path generation. In IEEE Workshop on RTL ATPG and DfT, Jaipur, IN, 2011.

[W33]

A. Spilla, I. Polian, J. Müller, M. Lewis, V. Tomashevich, B. Becker, and W. Bur-
gard. Run-time soft error injection and testing of a microprocessor using FPGAs.
In GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Syste-
men”, Passau, D, 2011.

[W32]

A. Paler, I. Polian, and J.P. Hayes. Tomographic testing and validation of probabilistic
circuits. In GI/GMM/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen”, Passau, D, 2011.

[W31]

P. Krause and I. Polian. Adaptive voltage over-scaling for resilient applications. In IEEE
Workshop on Reliability-Aware System Design and Test, Bangalore, IN, 2010.

[W30]

K.P. Ganeshpure, I. Polian, S. Kundu, and B. Becker. Reducing temperature variability
by routing heat pipes. In DATE Workshop on Process Variability, Nice, FR, 2009 (Poster).

[W29]

A. Czutro, B. Becker, and I. Polian. Performance evaluation of SAT-based ATPG on
multi-core architectures. In Workshop on Many-Cores, Delft, NL, 2009.

[W28]

I. Polian, S.M. Reddy, I. Pomeranz, X. Tang, and B. Becker. No free lunch in soft error
protection? In Workshop on Dependable and Secure Nanocomputing , Anchorage, AK, USA,
2008.

[W27]

A. Czutro, I. Polian, M. Lewis, P. Engelke, S. Reddy, and B. Becker. TIGUAN: Thread-
parallel Integrated test pattern Generator Utilizing satisfiability ANalysis. In edaWorkshop,
Hannover, D, 2008 (Poster).

[W26]

S. Spinner, I. Polian, P. Engelke, B. Becker, M. Keim, and W.-T. Cheng. Automatic test
pattern generation for interconnect open defects. In GI/ITG Workshop “Testmethoden und
Zuverlässigkeit von Schaltungen und Systemen”, Vienna, A, 2008.

[W25]

P. Engelke, I. Polian, J. Schloeffel, and B. Becker. Resistive bridging fault simulation of in-
dustrial circuits. In GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen”, Vienna, A, 2008.

[W24]

I. Polian, J.P. Hayes and B. Becker. Cost-efficient circuit hardening based on critical soft
error rate. In IEEE Workshop on RTL ATPG and DfT, Beijing, CN, 2007.

[W23]

J.P. Hayes, I. Polian, and B. Becker. A model for transient faults in logic circuits. In
IEEE Int’l Design and Test Workshop, Dubai, UAE, 2006.

[W22]

P. Engelke, I. Polian, H. Manhaeve, M. Renovell, and B. Becker. Delta-IDDQ testing of
resistive short defects. In IEEE Int’l Workshop on Current and Defect-Based Testing, Santa
Clara, CA, 2006.

[W21]

I. Polian, B. Becker, M. Nakasato, S. Ohtake, and H. Fujiwara. Period of grace: A
new paradigm for efficient soft error hardening. In GI/ITG Workshop “Testmethoden und
Zuverlässigkeit von Schaltungen und Systemen”, Freiburg, D, 2006.

[W20]

S. Spinner, J. Bartolomeyczik, B. Becker, M. Doelle, O. Paul, I. Polian P. Roth, K. Seitz,
and P. Ruther. Electromechanical reliability testing of three-axial force sensors. In GI/ITG
Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Freiburg, D,
2006. (poster)

[W19]

J. Reineke, B. Wachter, S. Thesing, R. Wilhelm, I. Polian, J. Eisinger, and B. Becker. A
definition and classification of timing anomalies. In Int’l Workshop on Worst-Case Execution
Time (WCET) Analysis, Dresden, D, 2006.

[W18]

I. Polian and H. Fujiwara. Functional constraints vs. test compression in scan-based delay
testing. In IEEE Int’l GHz/Gbps Test Workshop, pages 91–100, Austin, TX, USA, 2005.

[W17]

M. Doelle, S. Spinner, P. Ruther, I. Polian, O. Paul, and B. Becker. A system for deter-
mining the impact of mechanical stress on the reliability of MEMS. In IEEE European Test
Symp., pages 57–61, Tallinn, EST, 2005. (poster)

[W16]

J.P. Hayes, I. Polian, T. Fiehn, and B. Becker. A family of logical fault models for reversible
circuits. In IEEE European Test Symp., pages 65–70, Tallinn, EST, 2005. (poster)

[W15]

S. Kundu, M.D.T. Lewis, I. Polian, and B. Becker. A soft error emulation system for
logic circuits. In GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen”, pages 10–14, Innsbruck, A, 2005.

[W14]

P. Engelke, V. Gherman, I. Polian, Y. Tang, H.-J. Wunderlich, and B. Becker. Sequence
length, area cost and non-target defect coverage tradeoffs in deterministic logic BIST. In
IEEE Int’l Workshop on Current and Defect-Based Testing, pages 43–48, Palm Springs,
CA, USA, 2005.

[W13]

I. Polian, B. Becker, and A. Czutro. Compression methods for path delay fault test pair
sets: a comparative study. In IEEE European Test Symp., pages 263–264, Ajaccio, FR, 2004.
(poster)

[W12]

Y. Tang, H.-J. Wunderlich, H. Vranken, F. Hapke, M. Wittke, P. Engelke, I. Polian, and
B. Becker. X-masking during logic BIST and its impact on defect coverage. In IEEE Int’l
Workshop on Test Resource Partitioning, Napa Valley, CA, USA, 2004.

[W11]

P. Engelke, I. Polian, M. Renovell, and B. Becker. Automatic test pattern generation
for resistive bridging faults. In IEEE Int’l Workshop on Current and Defect-Based Testing,
pages 89–94, Napa Valley, CA, USA, 2004.

[W10]

B. Becker, M. Behle, F. Eisenbr /and, M. Fränzle, M. Herbstritt, C. Herde, J. Hoffmann,
D. Kröning, B. Nebel, I. Polian, and R. Wimmer. Bounded model checking and inductive
verification of hybrid discrete-continuous systems. In ITG/GI/GMM-Workshop “Methoden
und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Syste-
men”, pages 65 – 75, Kaiserslautern, D, 2004.

[W9]

P. Engelke, I. Polian, M. Renovell, B. Seshadri, and B. Becker. The pros and cons of
very-low-voltage testing: an analytical view. In GI/ITG Workshop “Testmethoden und
Zuverlässigkeit von Schaltungen und Systemen”, pages 149–153, Dresden, D, 2004.

[W8]

I. Polian and B. Becker. Reducing ATE cost in system-on-chip test. In IEEE Int’l Workshop
on Test Resource Partitioning, Napa Valley, CA, USA, 2003.

[W7]

P. Engelke, I. Polian, M. Renovell, and B. Becker. Simulating resistive bridging and stuck-
at faults. In IEEE Int’l Workshop on Current and Defect-Based Testing, pages 49–56, Napa
Valley, CA, USA, 2003.

[W6]

I. Polian, W. Günther, and B. Becker. The case for 2-POF. In ITG/GI/GMM-Workshop
“Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen
und Systemen”, Bremen, D, 2003.

[W5]

I. Polian, and B. Becker. Optimal bandwidth allocation in concurrent SoC test under pin
number constraints. In IEEE Workshop on RTL ATPG and DfT, Guam, USA, 2002.

[W4]

I. Polian, I. Pomeranz, and B. Becker. Exact computation of maximally dominating faults
and its application to n-detection tests. In IEEE European Test Workshop, Korfu, GR, 2002.
(poster)

[W3]

J. Bradford, H. Delong, I. Polian, and B. Becker. Realistic fault simulation in an indus-
trial setting. In GI/ITG Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und
Systemen”, Bad Herrenalb, D, 2002.

[W2]

I. Polian and B. Becker. Multiple scan chain design for two-pattern testing. In IEEE Latin
American Test Workshop, pages 156–161, Cancun, MX, 2001.

[W1]

I. Polian, W. Günther, and B. Becker. Efficient pattern-based verification of connections to intellectual property cores. In ITG/GI/GMM-Workshop “Methoden und Beschrei-
bungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen”, pages
I:111–120, Meissen, D, 2001.

Tutorials, Panels, Special Sessions

[T24]

“Security of emerging architectures”. Special Session co-organizer. Int’l Conf. on CAD,
San Diego, CA, USA, 2018.

[T23]

“Funding hardware security research: Taxpayer’s money to support malicious hackers?”
Panel organizer. Int’l Verification and Security Workshop, Platja d’Aro, ES, 2018.

[T22]

“Controlled fault injection: wishful thinking, thoughtful engineering, or just luck?” Pan-
elist. Workshop on Fault Diagnosis and Tolerance in Cryptography, Taipeh, TW, 2017.

[T21]

“Secure multi-processors systems-on-chip for critical applications.” Special Session co-
organizer. IEEE Conf. on System-on-Chip Design, Munich, D, 2017.

[T20]

“DFT vs. security – Is it a contradiction? How can we get the best of both worlds?”
Panelist. IEEE Int’l Verification and Security Workshop, Sant Feliu de Guixols, ES, 2016.

[T19]

“Test of secure devices”. TRUDEVICE Training School on Trustworthy Manufacturing
and Utilization of Secure Devices, Leukerbad, CH, 2016.

[T18]

“Emerging probabilistic circuits from stochastic to quantum: Will they scale?” Special
Session organizer. ACM/IEEE Design Automation Conf., San Francsco, CA, USA, 2015.

[T17]

“Counterfeit IC identification: How can test help?” Hot topic organizer. IEEE VLSI Test
Symp., Berkeley, CA, USA, 2013.

[T16]

“Current testing: Dear or alive?” Panelist. IEEE European Test Symp., Avignon, F, 2013.

[T15]

“Fault-based attacks on cryptographic hardware.” Embedded tutorial presenter. IEEE
Int’l Symp. on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Kar-
lowy Vary, CZ, 2013.

[T14]

“Quantum Informatics: Classical circuit synthesis, resource optimisation and benchmark-
ing.” Special session organizer. IEEE Asian Test Symp., Niigata, J, 2012.

[T13]

“Cross-layer reliability.” Special topic organizer. Int’l Workshop on Impact of Low-Power
Design on Test and Reliability, Annecy, FR, 2012.

[T12]

“Adaptive techniques for energy-reliability trade-offs.” Special topic organizer. Int’l Work-
shop on Impact of Low-Power Design on Test and Reliability, Trondheim, NO, 2011.

[T11]

“Volume diagnosis: Power in numbers?” Panel organizer and moderator. IEEE Workshop
on Reliability-Aware System Design and Test, Chennai, IN, 2011.

[T10]

“Testing nanoelectronic circuits under massive statistical process variations.” Special ses-
sion organizer. IEEE Asian Test Symp., Shanghai, CN, 2010.

[T9]

“Massive statistical process variations: A grand challenge for testing nanoelectronic circuits.”
Special session organizer. Intl Workshop on Dependable and Secure Nanocomputing, Chicago,
IL, USA, 2010.

[T8]

“Searching high and low for the right test.” Special session organizer. Int’l Workshop on
Impact of Low-Power Design on Test and Reliability, Prague, CZ, 2010.

[T7]

“Low-power test and noise-aware test: Foes or friends?” Panel organizer. IEEE VLSI Test
Symp., Santa Cruz, CA, USA, 2010.

[T6]

“End of CMOS roadmap – reliability and test challenges.” Panel organizer and moderator.
IEEE Workshop on Reliability-Aware System Design and Test, Bangalore, IN, 2010.

[T5]

“Test of power supply noise – causes, effects and testing.” Tutorial presenter. Int’l Workshop
on Impact of Low-Power Design on Test and Reliability, Sevilla, E, 2009.

[T4]

“Benchmarking academic DFT tools on the OpenSparc microprocessor.” Panelist. Int’l Test
Conf., Santa Clara, CA, USA, 2008.

[T3]

“Defect-tolerance, error-tolerance: which way to go? How?” Panelist. IEEE Workshop on
RTL ATPG and DfT, Beijing, CN, 2007.

[T2]

“Error-tolerance: Are good-enough chips good-enough?” Panel organizer and moderator.
IEEE European Test Symp., Freiburg, D, 2007.

[T1]

“Soft errors in micro and nanoelectronics.” Embedded tutorial presenter. GMM/GI/ITG
Reliability and Design Conf., Munich, D, 2007.

Invited Presentations (Not refereed)

1.

“Hardware security and test: Friends or enemies?” Keynote at the International Symposium
on Dependable Integrated Systems, Fukuoka, November 2016.

2.

“Hardware Trojans: An emerging threat for the Internet of Things”. Universita della
Svizzera Italiana, Lugano, October 2016 (Host: Dr. Francesco Regazzoni).

3.

“Hardware Trojans: An emerging threat for the Internet of Things”. EPFL Summer Re-
search Institute, Lausanne, June 2016 (Host: Prof. Brian Ford).

4.

“Hardware Trojans in early design steps: An emerging threat”. Dagstuhl Seminar “Hardware
Security”, May 2016.

5.

“Paradigm shifts in Electronics”. FRIAS lectures series “Paradigm Shifts in Science”,
Freiburg Institute of Advanced Studies, May 2016 (Host: Prof. Bernd Kortmann).

6.

“Parametric Trojans for fault-based attacks on cryptographic hardware”. RSS Management
Committee Meeting, October 2015 (Host: Prof. Ulf Schlichtmann).

7.

“Parametric Trojans for fault-based attacks on cryptographic hardware”. Bar-Ilan Univer-
sity, Ramat Gan, Israel, April 2015 (Host: Dr. Osnat Keren).

8.

“Parametric Trojans for fault-based attacks on cryptographic hardware”. University of Mas-
sachusetts, Amherst, USA, April 2014 (Hosts: Prof. Sandip Kundu, Prof. Israel Kundu and
Prof. Wayne Burleson).

9.

“Implications of extreme variability on architecture and test”. Dagstuhl NSF/SRC/DFG
Joint Workshop “Bugs and Defects in Electronic Systems: The Next Frontier”, April 2013.

10.

“Towards scalable quantum computing: Algorithmic challenges”, National Institute of In-
formatics, Tokyo, Japan, March 2013 (Hosts: Prof. Kae Nemoto and Prof. Simon Devitt).

11.

“Towards a cross-layer strategy against fault-based attacks”. Dagstuhl seminar “Verifying
Reliability”, August 2012.

12.

“Advanced test generation techniques for non-standard fault models”. Kyushu Institute of
Technology, Iizuka, Japan, Febr /uary 2012 (Host: Prof. Xiaoqing Wen).

13.

“Advanced test generation techniques for non-standard fault models”. Synopsys Inc., Moun-
tain View, USA, September 2011 (Host: Dr. Alodeep Sanyal).

14.

“Energy-reliability trade-offs in nanoscale electronics”. University of Frankfurt, Germany,
June 2011 (Host: Prof. Isolde Adler).

15.

“Adaptive voltage over-scaling for resilient applications”. University of Michigan, Ann Ar-
bor, USA, June 2010 (Host: Prof. John P. Hayes).

16.

“Test and reliability of nanoscale electronic systems: next-generation solutions for next-
generation challenges”. University of Southern California, Los Angeles, USA, October 2008
(Host: Prof. Dr. Sandeep Gupta).

17.

“Test, verification and validation of products”. Endress & Hauser Flowtec, Reinach, Switzer-
land, May 2007 (Host: Dr. Ulrich Kaiser).

18.

“Resource-constrained error handling in digital circuits”. Intel Santa Clara, USA, May 2007
(Host: Dr. Abhijit Jas).

19.

“Transient-error tolerance”. South European Test Seminar, Sestriere, Italy, March 2006.

20.

“Transient-error tolerance”. Nara Institute of Science and Technology (NAIST), Nara,
Japan, November 2006 (Host: Prof. Hideo Fujiwara).

21.

“Transient-error tolerance”. Yale University, New Haven, USA, October 2006 (Host: Prof.
Yiorgos Makris).

22.

“Power droop in high-performance ICs and a screening strategy”. AMD Boston Design
Center, Acton, USA, October 2006 (Host: Dr. Thomas Clouqueur).

23.

“Power droop in high-performance ICs and a screening strategy”. University of Mas-
sachusetts, Amherst, USA, September 2006 (Host: Prof. Sandip Kundu).

24.

“Period of grace: A new paradigm for efficient soft error hardening”. South European Test
Seminar, Neustift im Stubaital, Austria, March 2006.

25.

“Period of grace: A new paradigm for efficient soft error hardening”. Freiburg-Innsbruck-
Paderborn-Stuttgart Workshop, Freudenstadt, November 2005.

26.

“Test & diagnosis in nanoscale technologies”. Tokyo Metropolitan University, Tokyo, Japan,
October 2005 (Host: Prof. Kazuhiko Iwasaki).

27.

“Test & diagnosis in nanoscale technologies”. Osaka Gakuin University, Osaka, Japan,
September 2005 (Host: Prof. Kozo Kinoshita).

28.

“Soft errors: The fourth dimension”. Nara Institute of Science and Technology (NAIST),
Nara, Japan, September 2005 (Host: Prof. Hideo Fujiwara).

29.

“Test & diagnosis in nanoscale technologies”. Kyushu Institute of Technology, Fukuoka,
Japan, September 2005 (Host: Prof. Seiji Kajihara).

30.

“Test & diagnosis in nanoscale technologies”. Nara Institute of Science and Technology
(NAIST), Nara, Japan, August 2005 (Host: Prof. Hideo Fujiwara).

31.

“Test & diagnosis in nanoscale technologies”. Annual Meeting of the Professorial Advisory
Board of the German Informatics Society (GIBU), Dagstuhl, Germany, March 2005 (four of
the finalists of the GI Best Dissertations 2003 Award were invited).

32.

“Non-concurrent BIST for soft error detection”. South European Test Seminar, St. Leon-
hard, Austria, March 2005.

33.

“Transient fault modeling and detection in dynamic noisy environments”. Freiburg-Inns-
bruck-Stuttgart Workshop, Innsbruck, Austria, December 2004.

34.

“The pros and cons of Very-Low-Voltage testing”. University of Michigan, Ann Arbor, USA,
October 2004 (Host: Prof. John P. Hayes).

35.

“The pros and cons of Very-Low-Voltage testing”. Stanford University, USA, April 2004
(Host: Prof. Edward McCluskey).

36.

“Maximally dominating faults and n-detection”. Freiburg-Innsbruck-Stuttgart Workshop,
Freiburg, November 2003.

37.

“System-on-a-chip test: an overview and a new result”. Princeton University, USA, Decem-
ber 2002 (Host: Prof. Niraj Jha).

38.

“System-on-a-chip test: an overview and a new result”. University of Wisconsin, Madison,
USA, December 2002 (Host: Prof. Kewal Saluja).

39.

“Maximally dominating faults and n-detection”. Purdue University, West Lafayette, USA,
November 2002 (Host: Prof. Irith Pomeranz).

40.

“Defect-based test”. Micronas GmbH, Freiburg, Germany, November 2001 (Host: Hartmut
Delong).

41.

“BIST for delay faults”. University of Iowa, Iowa City, USA, August 1999 (Host: Prof. Sud-
hakar Reddy).

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