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HOCOS - Current Research Projects

Algebraic Fault Attacks

Algebraic Fault Attacks

(funded by DFG; project start in Oktober 2015)  Project page

Cryptographic circuits are employed in mobile and embedded systems to protect sensitive information from unauthorized access and manipulation. Fault attacks circumvent the protection by injecting faults into the hardware implementation of the cryptographic function, thus manipulating the calculation in a controlled manner and allowing the attacker to derive protected data such as secret keys. A large number of fault attacks and counter-measures against such attacks were suggested in the last years. However, isolated techniques for each individual attack are no longer sufficient; a generic protective strategy is lacking.

The Algebraic Fault Attacks project focuses on the class of algebraic fault attacks, where the information used for cryptanalysis is represented by systems of polynomials. In order to understand the scope of such attacks and develop suitable counter-measures, techniques to conduct algebraic fault attacks will be developed.

 

RA - Current Research Projects

FAST – Reliability Assessment using „Faster-than-at-Speed Test“

Project Page: FAST – Reliability Assessment using „Faster-than-at-Speed Test“

An important problem in modern technology nodes in nano-electronics are early life failures, which often cause recalls of shipped products and incur high costs.  An important root cause of such failures are marginal circuit structures, which pass a conventional manufacturing test, but are not able to cope with the later workload and stress in the field.  Such structures can be identified on the basis of non-functional indicators, in particular by testing the timing behavior.  For an effective and cost-efficient test of these indicators, the FAST project investigates novel scan designs and built-in self-test strategies for circuits, which can operate at frequencies beyond the functional specification to detect small deviations of the nominal timing behavior and thus potential early life failures.

since 2.2017, DFG-Project: WU 245/19-1   

SHIVA: Secure Hardware for Information Processing

Project page: SHIVA: Sichere Hardware in der Informationsverarbeitung

In the project „SHIVA: Secure Hardware for Information Processing“, coordinated by Prof. Dr. Wunderlich (Institut für Technische Informatik), novel design and verification methods are researched and developed to increase and assure the security of microelectronic hardware, used for instance in automobile, medical, or industrial applications. These methods will help to achieve increasing security requirements and prevent system manipulation, extraction of critical data or process information, and IP theft.

since 02.2016,    

ACCESS: Verification, Test, and Diagnosis of Advanced Scan Infrastructures

Project page: ACCESS: Verification, Test, and Diagnosis of Advanced Scan Infrastructures

VLSI designs incorporate specialized instrumentation for post-silicon validation and debug, volume test and diagnosis, as well as in-field system maintenance. Due to the increasing complexity, however, the embedded infrastructure and flexible access mechanisms such as Reconfigurable Scan Networks (RSNs) themselves become a dependability bottleneck.

While efficient verification, test, and diagnosis techniques exist for combinational and some classes of sequential circuits, Reconfigurable Scan Networks (RSNs) still pose a serious challenge. RSNs are controlled via a serial interface and exhibit deeply sequential behavior (cf. IJTAG, IEEE P1687). Due to complex combinational and sequential dependencies, RSNs are beyond the capabilities of existing algorithms for verification, test, and diagnosis which were developed for classical, non-reconfigurable scan networks. The goal of ACCESS is to establish a methodology for efficient verification, test and diagnosis of RSNs to meet stringent reliability, safety and security goals.

since 08.2014, DFG-Project: WU 245/17-1    

PARSIVAL: Parallel High-Throughput Simulations for Efficient Nanoelectronic Design and Test Validation

Project page: PARSIVAL: Parallel High-Throughput Simulations for Efficient Nanoelectronic Design and Test Validation

Design and test validation is one of the most important and complex tasks within modern semi-conductor product development cycles. The design validation process analyzes and assesses a developed design with respect to certain validation targets to ensure its compliance with given specifications and customer requirements. Test validation evaluates the defect coverage obtained by certain test strategies and assesses the quality of the products tested and delivered. The validation targets include both, functional and non-functional properties, as well as the complex interactions and interdependencies between them. The validation means rely mainly on compute-intensive simulations which require more and more highly parallel hardware acceleration.

In this project novel methods for versatile simulation-based VLSI design and test validation on high throughput data-parallel architectures will be developed, which enable a wide range of important state-of-the-art validation tasks for large circuits. In general, due to the nature of the design validation processes and due to the massive amount of data involved, parallelism and throughput-optimization are the keys for making design validation feasible for future industrial-sized designs. The main focus and key features lie in the structure of the simulation model, the abstraction level and the used algorithms, as well as their parallelization on data-parallel architectures. The simulation algorithms should be kept simple to run fast, yet accurate enough to produce acceptable and valuable data for cross-layer validation of complex digital systems.

since 10.2014, DFG-Project: WU 245/16-1    

Simulation on Reconfigurable Heterogeneous Computer Architectures

Project page: Simulation on Reconfigurable Heterogeneous Computer Architectures

Since the beginning of the DFG Cluster of Excellence "Simulation Technology" (SimTech) at the University of Stuttgart in 2008, the Institute of Computer Architecture and Computer Engineering (ITI, RA) is an active part of the research within the Stuttgart Research Center for Simulation Technology (SRC SimTech). The institute's research includes the development of fault tolerant simulation algorithms for new, tightly-coupled many-core computer architectures like GPUs, the acceleration of existing simulations on such architectures, as well as the mapping of complex simulation applications to innovative reconfigurable heterogeneous computer architectures

Within the research cluster, Hans-Joachim Wunderlich acts as a principal investigator (PI) and he co-coordinates the research activities of the SimTech Project Network PN2 "High-Performance Simulation across Computer Architectures". This project network is unique in terms of its interdisciplinary nature and its interfaces between the participating researchers and projects. Scientists from computer science, chemistry, physics and chemical engineering work together to develop and provide new solutions for some of the major challenges in simulation technology. The classes of computational problems treated within project network PN2 comprise quantum mechanics, molecular mechanics, electronic structure methods, molecular dynamics, Markov-chain Monte-Carlo simulations and polarizable force fields.

06.2008 - 10.2017, SimTech Cluster of Excellence   

OTERA: Online Test Strategies for Reliable Reconfigurable Architectures

Project page: Online Test Strategies for Reliable Reconfigurable Architectures

Dynamically reconfigurable architectures enable a major acceleration of diverse applications by changing and optimizing the structure of the system at runtime. Permanent and transient faults threaten the correct operation of such an architecture. This project aims to increase dependability of runtime reconfigurable systems by a novel system-level strategy for online tests and online adaptation to an impaired state. This will be achieved by (a) scheduling such that tests for reconfigurable resources are executed with minimal performance impact, (b) resource management such that partially faulty resources are used for components which do not require the faulty elements, and (c) online monitoring and error checking. To ensure reliable runtime reconfiguration, each reconfiguration process is thoroughly tested by a novel and efficient combination of online structural and functional tests. Compared to existing fault-tolerance approaches, our proposal avoids the large hardware overhead of structural redundancy schemes. The saved resources are available for further application acceleration. Still, the proposed scheme covers faults in the fabric, in the reconfigured application logic and errors in the process of reconfiguration. 

10.2010 - 06.2017, DFG-Project: WU 245/10-1, 10-2, 10-3   

ROBUST: Robust Electronic System Design

Projectpage: ROBUST

ROBUST researches new methods and procedures for designing robust nano-electronic systems. The project abstracts and defines quantitative measures of robustness, which are then employed for guiding and assessing static and dynamic optimization of robustness. The results of ROBUST are methods and prototype tools that enable early consideration of robustness in the context of a top-down system design flow. Our contribution to ROBUST lies in assessing robustness on system level based on directed and randomized fault injection with SystemC. 

NATSIM: Native and Adaptive Transaction Level Simulation of Embedded Systems

In NATSIM we develop formalisms, novel modeling techniques and efficient simulation mechanisms for complex embedded hardware-software systems. Traditionally, TLM languages, methodologies and simulation environments have focused on systems with fixed component functionality and static communication architectures. In NATSIM we deal with run-time reconfigurable and self-adaptive embedded systems. Additionally, existing TLM simulation environments are purely sequential. NATSIM aims at enabling parallel TLM simulation environments with multi-core simulation hosts and clusters. 

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