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< Parametric Delay Modeling in Gate Level Time Simulation

Variation aware marginal defects detection

Category: Open Seminar - Rechnerarchitektur

09:00-10:00, Bad Herrenalb, M. Sc. Zahra Paria Najafi Haghi, Institut für Technische Informatik

As devices can work properly in the beginning, weak structures must be identified by analyzing the non-functional circuit behavior with the help of appropriate observables. Besides power consumption, the circuit timing is one of the most important reliability indicators. In particular, small delay faults may indicate marginal hardware that can degrade further under stress and make a failure for a circuit when works in the field. However, these Small Delay Faults can be “hidden” at nominal test frequency. Therefore, conventional approaches for testing reach their limitations and new methods should be applied.

In this work, different defects in FinFET technology which cause extra delay to the circuit will be investigated and modeled. A Faulty FinFET cell will be tested under different circumstances which can effect the duration of the Delay Faults. These varying circumstances means giving different values to the operation point- here Voltage and Temperature- and investigating their effect on Small Delay Faults. On the other hand, varying operation point has different impact on cells with Process Variation and without SDF, which should pass the test. This different impact on the observables- here propagation delay- gives the opportunity to classify cells with SDFs and cells which are delayed due to the Process Variation.


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