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01.08.19

Parametric Delay Modeling in Gate Level Time Simulation

Kategorie: Open Seminar - Rechnerarchitektur

09:20 - 10:20, Bad Herrenalb, Dipl. Inf. Eric Schneider, Institut für Technische Informatik


Timing-accurate simulation poses a serious bottleneck in design and test validation of today's nano-electronic circuits due to high computational efforts.With systems running under different operating conditions, i.e., adaptive voltage and frequency scaling (AVFS) or ambient temperatures, traditional time simulation approaches based on static delays cannot be used anymore for meaningful design space exploration, since they lack the ability to consider parameter dependencies.

However, adding such dependencies into the delay models further increases the computational effort of time simulation to a point where the complexity cannot be handled without the use of efficient parallelization.

In this work, a massively parallel time simulation is presented that provides a compact multi-dimensional parametric delay modeling for design space exploration of AVFS-based systems.Analog simulation of standard cells is used as a preprocessing step to obtain gate delays under different operating points, which are then processed using statistical learning methods to derive delay kernels that compute the gate delays of each cell type during simulation.With the help of Graphics Processing Units and their computational power, the simulator is able to achieve highest simulation throughput with Billions of gate evaluations per second at full timing-accuracy consideration of parametric dependencies enabling large-scale design space exploration of AVFS-based systems for the first time.

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